Dual address encoding for logical-to-physical mapping
View Patent ↗Methods, systems, and devices for dual address encoding for logical-to-physical mapping are described. A memory device may identify a first physical address corresponding to a first logical block address generated by a host device and a second physical address corresponding to a second (consecutive) logical block address generated by a host device. The memory device may store the first physical address and second physical address in a single entry of a logical-to-physical mapping table that corresponds to the first logical block address. The memory device may transmit the logical-to-physical table to the host device for storage at the host device. The host device may subsequently transmit a single read command to the memory device that includes the first physical address and the second physical address based on the logical-to-physical table.
1. A method, comprising:
receiving, from a host device, a read command comprising:
a transfer length field indicating a quantity of two or more contiguous logical blocks of data to be returned; and
a value associated with a set of entries that comprise respective physical block addresses of the two or more contiguous logical blocks of data;
reading, by a memory device, the two or more contiguous logical blocks from the respective physical block addresses of the memory device based at least in part on the transfer length field and the set of entries; and
transmitting, to the host device, the two or more contiguous logical blocks of data in accordance with the read command.
2. The method of claim 1 , wherein the read command further comprises a logical block address of a first logical block of the two or more contiguous logical blocks of data and an entry containing a physical block address of the first logical block.
3. The method of claim 1 , further comprising:
receiving, from the host device, the set of entries comprising the respective physical block addresses of the two or more contiguous logical blocks of data; and
storing, by the memory device, the set of entries in association with the value.
4. The method of claim 1 , wherein a size of each of the two or more contiguous logical blocks of data is 4 kilobytes (kB).
5. The method of claim 1 , wherein a value of the transfer length field indicates a combined size of the two or more contiguous logical blocks of data.
6. The method of claim 1 , wherein each entry of the set of entries is maintained in a cache of the host device.
7. The method of claim 1 , wherein each entry of the set of entries has a length of 8 bytes.
8. A memory device, comprising:
a memory array; and
a controller coupled with the memory array and operable to cause the memory device to:
receive, from a host device, a read command comprising:
a transfer length field indicating a quantity of two or more contiguous logical blocks of data to be returned; and
a value associated with a set of entries that comprise respective physical block addresses of the two or more contiguous logical blocks of data;
read, by the memory device, the two or more contiguous logical blocks from the respective physical block addresses of the memory array based at least in part on the transfer length field and the set of entries; and
transmit, to the host device, the two or more contiguous logical blocks of data in accordance with the read command.
9. The memory device of claim 8 , wherein the read command further comprises a logical block address of a first logical block of the two or more contiguous logical blocks of data and an entry containing a physical block address of the first logical block.
10. The memory device of claim 8 , wherein the controller is further operable to cause the memory device to:
receive, from the host device, the set of entries comprising the respective physical block addresses of the two or more contiguous logical blocks of data; and
store, by the memory device, the set of entries in association with the value.
11. The memory device of claim 8 , wherein a size of each of the two or more contiguous logical blocks of data is 4 kilobytes (kB).
12. The memory device of claim 8 , wherein a value of the transfer length field indicates a combined size of the two or more contiguous logical blocks of data.
13. The memory device of claim 8 , wherein each entry of the set of entries is maintained in a cache of the host device.
14. The memory device of claim 8 , wherein each entry of the set of entries has a length of 8 bytes.
15. A method, comprising:
transmitting, by a host device, a set of entries comprising respective physical block addresses of two or more contiguous logical blocks of data;
transmitting, to a memory device, a read command comprising:
a transfer length field indicating a quantity of the two or more contiguous logical blocks of data to be returned; and
a value associated with the set of entries comprising the respective physical block addresses of the two or more contiguous logical blocks of data; and
receiving, from the memory device, the two or more contiguous logical blocks of data in accordance with the read command.
16. The method of claim 15 , wherein the read command further comprises a logical block address of a first logical block of the two or more contiguous logical blocks of data and an entry containing a physical block address of the first logical block.
17. The method of claim 15 , further comprising:
retrieving the set of entries from a cache of the host device before transmitting the set of entries to the memory device.
18. The method of claim 15 , wherein a size of each of the two or more contiguous logical blocks of data is 4 kilobytes (kB).
19. The method of claim 15 , wherein a value of the transfer length field indicates a combined size of the two or more contiguous logical blocks of data.
20. The method of claim 15 , wherein each entry of the set of entries has a length of 8 bytes.