Energy efficient digital to time converter (DTC) for edge computing
A spatially unrolled time domain (TD) architecture that includes an input and weight register having i inputs and j weights, where i corresponds with a number of delay lines for i neurons, and j corresponds with a number of processing elements (PEs) for each delay line of the i delay lines. An enable control register sends a global input pulse to i neurons, and each delay line of the i delay lines includes the corresponding j PEs for that delay line. Each PE includes a digital-to-time converter (DTC) that accepts a digital input and weight and generates a relative delay, each time delay within a given delay line contributing to an overall delay for the given delay line. i time-to-digital converters (TDCs). A readout register receives digital outputs from each of the i TDCs, and serially outputs a signal from each of the i delay lines based on the overall time delay for each of the i delay lines.
1 . A spatially unrolled time domain (TD) architecture, comprising:
an input and weight register having a matrix of i inputs and j weights, where i corresponds with a number of delay lines for i neurons, and j corresponds with a number of processing elements (PEs) for each delay line of the i delay lines;
an enable control register for sending a global input pulse to each of the i delay lines, wherein each delay line of the i delay lines includes the corresponding j PEs for that delay line, wherein each of the j PEs include a digital-to-time converter (DTC) such that there are j DTCs in each delay line, wherein each DTC of the j DTCs accepts a respective digital input and weight from the input and weight register, and wherein each DTC of the j DTCs in each delay line generates a time delay that is added to the global input pulse such that j time delays are added to the global input pulse of the delay line, wherein each DTC is a laddered inverter (LI) having complementary metal-oxide semiconductor (CMOS) inverters, causing each of the time delays that are each based a ratio of n-channel metal-oxide semiconductor (NMOS) versus p-channel metal-oxide semiconductor (PMOS) gate lengths;
a number of i time-to-digital converters (TDCs), each corresponding with a corresponding delay line and receiving an output from the corresponding delay line; and
a readout register that receives digital outputs from each of the i TDCs, and serially outputs a signal from each of the i delay lines based on an overall time delay for each of the i delay lines.
2 . The spatially unrolled TD architecture of claim 1 , wherein each weight is a 3-bit weight.
3 . The spatially unrolled TD architecture of claim 1 , further comprising a global reference delay line having j reference DTCs for generating j reference delays respectively corresponding to each DTC of the j DTCs in each of the i delay lines.
4 . The spatially unrolled TD architecture of claim 1 , further comprising a calibration stage having i calibration delay lines for calibrating each delay line, to account for process and temperature variations and tunes output delays.
5 . The spatially unrolled TD architecture of claim 1 , wherein each delay line includes a delay in the input pulse that is determined at least in part based on a sum of a dot product of inputs and weights, which is a result of delays generated by each of the DTCs in a corresponding delay line.
6 . The spatially unrolled TD architecture of claim 1 , wherein each input is a 1-bit binary input.
7 . A method of mapping a series of time delays in edge computing, comprising:
providing an input and weight register having a matrix of i inputs and j weights, where i corresponds with a number of delay lines for i neurons, and j corresponds with a number of processing elements (PEs) for each delay line of the i delay lines;
providing an enable control register for sending a global input pulse to each of the i delay lines, wherein each delay line of the i delay lines includes the corresponding j PEs for that delay line, wherein each the j PEs include a digital-to-time converter (DTC) such that there are j DTCs in each delay line, wherein each DTC of the j DTCs accepts a respective digital input and weight from the input and weight register, and wherein each DTC of the j DTCs in each delay line generates a time delay that is added to the global input pulse such that i time delays are added to the global input pulse of the delay line, wherein each DTC is a laddered inverter (LI) having complementary metal-oxide semiconductor (CMOS) inverters such that there are j LIs in each delay line, the LI generates the time delay for each respective DTC, wherein each time delay of the j time delays is based a ratio of n-channel metal-oxide semiconductor (NMOS) versus p-channel metal-oxide semiconductor (PMOS) gate lengths;
providing a number of i time-to-digital converters (TDCs), each corresponding with a corresponding delay line and receiving an output from the corresponding delay line; and
providing a readout register that receives digital outputs from each of the i TDCs, and serially outputs a signal from each of the i delay lines based on an overall time delay for each of the i delay lines.
8 . The method of claim 7 , wherein each weight is a 3-bit weight.
9 . The method of claim 7 , wherein each input is a 1-bit binary input.
10 . The method of claim 7 , further comprising providing a global reference delay line having j reference DTCs for generating j reference delays, each of the j reference delays respectively correspond to the j DTCs in each of the i delay lines.
11 . The method of claim 7 , further comprising providing a calibration stage having i calibration delay lines for calibrating each delay line, to account for process and temperature variations and tunes output delays.
12 . The method of claim 7 , wherein each delay line provides a delay to the global input pulse that is determined at least in part based on a sum of a dot product of inputs and weights, which is a result of delays generated by each of the j DTCs in a corresponding delay line.
13 . A system comprising:
a spatially unrolled (SU) time-domain (TD) architecture, the SU TD architecture comprising:
at least one delay line, wherein each delay line of the at least one delay line is a sequence of Digital-to-Time converters (DTC) and each DTC of the sequence of DTCs comprises a laddered inverter (LI) having complementary metal-oxide semiconductor (CMOS) inverters that causes a time delay that is based on a ratio of n-channel metal-oxide semiconductor (NMOS) versus p-channel metal-oxide semiconductor (PMOS) gate lengths.
14 . The system of claim 13 , wherein each delay line of the at least one delay line is configured to receive a respective input pulse, and wherein each DTC of the sequence of DTCs is configured to add the respective time delay to the respective input pulse, wherein each respective time delay is based on a dot product of an input and weight associated with the respective delay line.
15 . The system of claim 13 , further comprising a calibration stage having one or more calibration delay lines for calibrating each delay line, to account for process and temperature variations and tune output delays.
16 . The system of claim 13 , further comprising a global reference delay line having a sequence of one or more reference DTCs, wherein each reference DTC of the one or more reference DTCs generates a reference delay, and wherein a sum of DTCs in the sequence of DTCs is equal to a sum of reference DTCs in the sequence of reference DTCs.
17 . A method comprising:
providing at least one delay line, wherein each delay line of the at least one delay line is a sequence of Digital-to-Time converters (DTC) and each DTC of the sequence of DTCs comprises a laddered inverter (LI) having complementary metal-oxide semiconductor (CMOS) inverters that causes a time delay that is based on a ratio of n-channel metal-oxide semiconductor (NMOS) versus p-channel metal-oxide semiconductor (PMOS) gate lengths.
18 . The method of claim 17 , wherein each DTC of the sequence of DTCs is configured to add the respective time delay to an input pulse passing through each of the at least one delay line, wherein each respective time delay is based a dot product of an input and a weight associated with each DTC in the sequence of DTCs, wherein the at least one delay line is part of a spatially unrolled (SU) time-domain (TD) architecture.
19 . The method of claim 17 , further comprising providing a global reference delay line having a sequence of one or more reference DTCs, wherein each reference DTC of the one or more reference DTCs generates a reference delay, and wherein a sum of DTCs in the sequence of DTCs is equal to a sum of reference DTCs in the sequence of reference DTCs.
20 . The method of claim 19 , further comprising providing a plurality of calibration delay lines such that each of the at least one delay line and the global reference delay line has a calibration delay line, wherein each calibration delay line of the plurality of calibration delay lines accounts for process and temperature variations from its corresponding delay line and tunes output delays received from its corresponding delay line.