IP Library Granted Patent US 12,456,437
Granted Patent B2
US 12,456,437 · App. 18/235,994 · Granted Oct 28, 2025

Display device with drive circuit

Inventor: Tadayoshi Katsuta (Tokyo, JP)
Assignee: Magnolia White Corporation
G09G3/3677G09G2310/061G09G2320/0247G09G2320/046G09G2330/022
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Quick Facts
Patent No.
US 12,456,437
App. No.
18/235,994
Granted
Oct 28, 2025
Kind
B2
Abstract

A display device includes: a pixel, a scanning line, a signal line, and a drive circuit. The drive circuit includes: a gate driver configured to supply a scanning signal to a scanning line; a signal line selection circuit configured to supply a pixel signal to a signal line; and a display control circuit. The drive circuit includes: a first switch circuit configured to be turned on at first time in a power-off sequence to supply a first power supply voltage signal to the scanning line; a second switch circuit configured to be turned on at the first time to supply a GND potential to the signal line; and a reset circuit configured to maintain an ON state of the first and second switch circuits after control on the gate driver and the signal line selection circuit is stopped at second time after the first time.

Claims (60)

1. A display device comprising:

a pixel comprising a pixel transistor and a pixel electrode coupled to a first electrode of the pixel transistor;

a scanning line coupled to a gate of the pixel transistor;

a signal line coupled to a second electrode of the pixel transistor; and

a drive circuit configured to be supplied with a first power supply voltage signal of a positive value and a second power supply voltage signal of a negative value to drive the pixel transistor,

wherein the drive circuit comprises:

a gate driver configured to supply a scanning signal to the scanning line;

a signal line selection circuit configured to supply a pixel signal to the signal line; and

a display control circuit configured to control the gate driver and the signal line selection circuit,

wherein holding capacitance is provided between the pixel electrode and a common electrode supplied with a common potential lower than a GND potential in a display operation, and

wherein the drive circuit comprises:

a first switch circuit configured to be turned on at first time in a power-off sequence to supply the first power supply voltage signal to the scanning line;

a second switch circuit configured to be turned on at the first time to supply the GND potential to the signal line; and

a reset circuit configured to maintain an ON state of the first switch circuit and the second switch circuit after control on the gate driver and the signal line selection circuit is stopped at second time after the first time at which the first switch circuit and the second switch circuit are turned on.

2. The display device according to claim 1 , wherein

the reset circuit maintains the ON state of the first switch circuit and the second switch circuit for a predetermined period from the second time at which the control on the gate driver and the signal line selection circuit is stopped to time at which the first power supply voltage signal becomes equal to or lower than a threshold voltage of the pixel transistor.

3. The display device according to claim 1 , further comprising a driver IC including at least the display control circuit.

4. A display device comprising:

a pixel comprising a pixel transistor, a pixel electrode coupled to a first electrode of the pixel transistor, and a common electrode facing the pixel electrode;

a scanning line coupled to a gate electrode of the pixel transistor;

a signal line coupled to a second electrode of the pixel transistor;

a drive circuit configured

to be driven with start pulse signals, shift clock signals, reset signals, and power supply voltage signals,

to supply scanning signals to the scanning line and a pixel signal to the signal line in a display operation, and

to supply one of the power supply voltage signals to the scanning line and a ground potential to the signal line after the display operation and before a time at which the display device is turned off;

a first switch circuit included in the drive circuit, having a first switch transistor turned in accordance with the reset signals, and configured to supply the one of the power supply voltage signals to the scanning line; and

a second switch circuit included in the drive circuit, having a second switch transistor turned on in accordance with the reset signals, and configured to supply the ground potential to the signal line,

wherein the start pulse signals, the shift clock signals, and the power supply voltage signals become the ground potential after the display operation, and

the power supply voltage signals become the ground potential after the start pulse signals and the shift clock signals become the ground potential.

5. The display device according to claim 4 , wherein

the scanning signals become the ground potential after the display operation, and after the start pulse signals and the shift clock signals become the ground potential.

6. The display device according to claim 4 , wherein

the power supply voltage signals includes a first power supply voltage signal of a positive value and a second power supply voltage signal of a negative value, and

the first power supply voltage of the positive value is supplied to the scanning line after the display operation and before the first power supply voltage becomes the ground potential.

7. The display device according to claim 4 , wherein

a same reset signal of the reset signals is applied to a first gate electrode of the first switch transistor and a second gate electrode of the second switch transistor.

8. The display device according to claim 4 , wherein

the first and second switch transistors are configured to be turned on at a same time.

9. The display device according to claim 4 , wherein

the first and second switch transistors are configured to maintain the ON state after the start pulse signals and the shift clock signals become the ground potential.

10. The display device according to claim 9 , wherein

the first and second switch transistors are configured to maintain the ON state until the one of the power supply voltage signals become a threshold voltage of the pixel transistor.

11. The display device according to claim 4 , wherein

the drive circuit is configured to supply a signal that display a black image to the signal line after the display operation and before supplying the one of the power supply voltage signals to the scanning line.

12. The display device according to claim 4 , wherein

the second switch circuit has a third switch transistor,

a polarity of the second switch transistor is different from a polarity of the third switch transistor, and

the second and third switch transistors form a complementary circuit.

13. A display device comprising:

a display operation period;

a power-off sequence period after the display operation period and before the display device is turned off;

a pixel comprising a pixel transistor, a pixel electrode coupled to a first electrode of the pixel transistor;

a scanning line coupled to a gate electrode of the pixel transistor;

a signal line coupled to a second electrode of the pixel transistor; and

a drive circuit configured to receive start pulse signals and power supply voltage signals, to supply one of the power supply voltage signals to the scanning line in the power-off sequence period, and to supply a ground potential to the signal line in the power-off sequence period,

wherein the power supply voltage signals become the ground potential in the power-off sequence period after the start pulse signals become the ground potential in the power-off sequence period,

the drive circuit includes a first switch circuit and a second switch circuit,

the first switch circuit is configured to supply the one of the power supply voltage signals to the scanning line, and has a first switch transistor coupled to the scanning line,

the second switch circuit is configured to supply the ground potential to the signal line, and has a second switch transistor coupled to the signal line, and

the first and second transistors are configured to maintain the ON state until the one of the power supply voltage signals become a threshold voltage of the pixel transistor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 071793/0491 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2023
From: KATSUTA, TADAYOSHI
To: JAPAN DISPLAY INC.
Reel/Frame 064721/0758 →
Priority Claims (1)
JP 2022-131885 · Aug 22, 2022 · national
Continuity (1)
Related Publication 20240062734A1 · Feb 22, 2024
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