Granted Patent B2

US 12,652,002 · App. 18/255,443 · Granted Jun 9, 2026

Inventors: Jing Xu (Beijing, CN); Xiang Yu (Beijing, CN)

Assignee: SG MICRO CORP

H03F1/0233H03F3/45183H03F3/45273H03F3/45475

Abstract

Claims (53)

1 . A bandwidth adjustment circuit of an operational amplifier, comprising:

a bias current generation unit, which is connected to a bias current input terminal of the operational amplifier and used for supplying a bias current to the operational amplifier;

a current adjustment unit, which is connected to the bias current generation unit and an output terminal of the operational amplifier, respectively, and used for adjusting the bias current according to an output voltage of the operational amplifier to realize bandwidth adjustment on the operational amplifier,

wherein the current adjustment unit comprises an adjusting transistor, which is serially connected between the output terminal of the operational amplifier for providing the output voltage and a power supply terminal, to allow a first current flowing through the adjusting transistor to be adjusted according to the output voltage of the operational amplifier,

wherein the current adjustment unit is configured to adjust the bias current by shunting a current flow off from the bias current, the current flow is adjusted in accordance with the first current flowing through the adjusting transistor.

2 . The bandwidth adjustment circuit according to claim 1 , wherein the bias current generation unit comprises:

a first transistor and a second transistor forming a current mirror structure, wherein a source of the first transistor and a source of the second transistor are both connected to the power supply terminal, a gate and a drain of the first transistor are both connected to a gate of the second transistor, and a drain of the second transistor is connected to the bias current input terminal of the operational amplifier;

a first current source, connected between the drain of the first transistor and a reference ground.

3 . The bandwidth adjustment circuit according to claim 2 , wherein a ratio between a width-to-length ratio of the first transistor and a width-to-length ratio of the second transistor is 1:1.

4 . The bandwidth adjustment circuit according to claim 3 , wherein the first transistor and the second transistor are both PMOS transistors.

5 . The bandwidth adjustment circuit according to claim 1 , wherein the current adjustment unit comprises:

a third transistor and a fourth transistor forming a current mirror structure, wherein a drain of the third transistor is connected to the bias current input terminal of the operational amplifier, a gate of the third transistor is connected to both of a gate and a drain of the fourth transistor, and a source of the third transistor and a source of the fourth transistor is connected to a reference ground;

a fifth transistor, which has a drain connected to the power supply terminal through a second current source, and has a source connected to the reference ground;

a sixth transistor serving as the adjusting transistor, which has a gate connected to both of a gate and the drain of the fifth transistor and has a source connected to the output terminal of the operational amplifier;

a seventh transistor and an eighth transistor forming a current mirror structure, wherein a source of the seventh transistor and a source of the eighth transistor are both connected to the power supply terminal, a gate electrode of the seventh transistor is connected to both of a gate and a drain electrode of the eighth transistor, a drain of the seventh transistor is connected to the drain electrode of the fourth transistor, and a drain of the eighth transistor is connected to a drain electrode of the sixth transistor.

6 . The bandwidth adjustment circuit according to claim 5 , wherein a ratio between a width-to-length ratio of the third transistor and a width-to-length ratio of the fourth transistor is n:1;

a ratio between a width-to-length ratio of the fifth transistor and a width-to-length ratio of the sixth transistor is 1:1;

a ratio between a width-to-length ratio of the seventh transistor and a width-to-length ratio of the eighth transistor is 1:1,

where n is a positive number.

7 . The bandwidth adjustment circuit according to claim 6 , wherein the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are all NMOS transistors;

the seventh transistor and the eighth transistor are both PMOS transistors.

8 . A bandwidth adjustment method of an operational amplifier, comprising:

providing a bias current to the operational amplifier based on a current source;

adjusting the bias current according to an output voltage of the operational amplifier, so as to realize bandwidth adjustment on the operational amplifier,

wherein adjusting the bias current according to an output voltage of the operational amplifier comprises:

adjusting a first current flowing through an adjusting transistor according to the output voltage of the operational amplifier, wherein the adjusting transistor is serially connected between an output terminal of the operational amplifier for providing the output voltage and a power supply terminal; and

adjust the bias current by shunting a current flow off from the bias current, wherein the current flow is adjusted in accordance with the first current flowing through the adjusting transistor.

9 . The bandwidth adjustment method according to claim 8 , wherein step of providing the bias current to the operational amplifier based on the current source comprises:

generating a first mirror current on a second branch of a first current mirror circuit based on the current source arranged on a first current branch of the first current mirror circuit;

supplying the first mirror current to a bias current input terminal of the operational amplifier, wherein the current flow is shunt off at the bias current input terminal.

10 . The bandwidth adjustment method according to claim 9 , wherein

the first current is generated on a first current branch of a second current mirror circuit comprising the adjusted transistor

and a second mirror current, serving as the current flow, is provided on a second current branch of the second current mirror circuit;

wherein, the first mirror current is equal to a sum of the bias current and the second mirror current.

11 . A bandwidth adjustment circuit of an operational amplifier, comprising:

a bias current generation unit, which is connected to a bias current input terminal of the operational amplifier and used for supplying a bias current to the operational amplifier;

a current adjustment unit, which is connected to the bias current generation unit and an output terminal of the operational amplifier, respectively, and used for adjusting the bias current according to an output voltage of the operational amplifier to realize bandwidth adjustment on the operational amplifier,

wherein the current adjustment unit comprises:

a third transistor and a fourth transistor forming a current mirror structure, wherein a drain of the third transistor is connected to the bias current input terminal of the operational amplifier, a gate of the third transistor is connected to both of a gate and a drain of the fourth transistor, and a source of the third transistor and a source of the fourth transistor is connected to a reference ground;

a fifth transistor, which has a drain connected to a power supply terminal through a second current source, and has a source connected to the reference ground;

a sixth transistor, which has a gate connected to both of a gate and the drain of the fifth transistor and has a source connected to the output terminal of the operational amplifier;

a seventh transistor and an eighth transistor forming a current mirror structure, wherein a source of the seventh transistor and a source of the eighth transistor are both connected to the power supply terminal, a gate electrode of the seventh transistor is connected to both of a gate and a drain electrode of the eighth transistor, a drain of the seventh transistor is connected to the drain electrode of the fourth transistor, and a drain of the eighth transistor is connected to a drain electrode of the sixth transistor.

12 . The bandwidth adjustment circuit according to claim 11 , wherein the bias current generation unit comprises:

a first transistor and a second transistor forming a current mirror structure, wherein a source of the first transistor and a source of the second transistor are both connected to the power supply terminal, a gate and a drain of the first transistor are both connected to a gate of the second transistor, and a drain of the second transistor is connected to the bias current input terminal of the operational amplifier;

a first current source, connected between the drain of the first transistor and a reference ground.

13 . The bandwidth adjustment circuit according to claim 12 , wherein a ratio between a width-to-length ratio of the first transistor and a width-to-length ratio of the second transistor is 1:1.

14 . The bandwidth adjustment circuit according to claim 11 , wherein the first transistor and the second transistor are both PMOS transistors.

15 . The bandwidth adjustment circuit according to claim 11 , wherein a ratio between a width-to-length ratio of the third transistor and a width-to-length ratio of the fourth transistor is n:1;

a ratio between a width-to-length ratio of the fifth transistor and a width-to-length ratio of the sixth transistor is 1:1;

a ratio between a width-to-length ratio of the seventh transistor and a width-to-length ratio of the eighth transistor is 1:1,

where n is a positive number.

16 . The bandwidth adjustment circuit according to claim 11 , wherein the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are all NMOS transistors;

the seventh transistor and the eighth transistor are both PMOS transistors.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (16)