Power semiconductor module, method for manufacturing the same and electrical converter
A power semiconductor module ( 34 ), comprising a substrate ( 12 ) which carries a plurality of power semiconductor devices ( 10 ), wherein the plurality of power semiconductor devices ( 10 ) comprises a first group of power semiconductor devices ( 10 ) and a second group of at least one power semiconductor device ( 10 ). The first group of power semiconductor devices ( 10 ) consists of at least two non-damaged power semiconductor devices ( 10 b, 10 c ), and the second group of power semiconductor devices ( 10 ) consists of at least one damaged power semiconductor device ( 10 a ). The at least two non-damaged power semiconductor devices ( 10 b, 10 c ) are electrically interconnected in a parallel configuration, and the second group of at least one power semiconductor device ( 10 ) is electrically separated from the members of the first group of power semiconductor devices ( 10 ). The disclosure further relates to an electrical converter and a method for manufacturing a power semiconductor module ( 34 ).
1 . A power semiconductor module, comprising a substrate which carries a plurality of power semiconductor devices, wherein the plurality of power semiconductor devices comprises a first group of power semiconductor devices and a second group of at least one power semiconductor device,
wherein the first group of power semiconductor devices comprises non-damaged power semiconductor devices and at least one power semiconductor device which is provided with a measuring arrangement, wherein the measuring arrangement comprises at least one measuring point for measuring at least one of electronic, magnetic and temperature properties of the at least one power semiconductor device, the at least one measuring point being formed by a pre-determined breaking point corresponding to a position of an electrical interconnection structure having a reduced thickness and/or width, and
wherein the second group of power semiconductor devices comprises at least one damaged power semiconductor device,
wherein at least two non-damaged power semiconductor devices are electrically interconnected in a parallel configuration, and
wherein the second group of at least one power semiconductor device is electrically separated from members of the first group of power semiconductor devices,
wherein at least one electrical connection between the at least one damaged power semiconductor device and the non-damaged power semiconductor devices is present.
2 . The power semiconductor module according to claim 1 , wherein electrical connections from a non-damaged power semiconductor device to an emitter and a gate of the at least one damaged power semiconductor device are interrupted, but an electrical connection from a non-damaged power semiconductor device to another contact of the at least one damaged power semiconductor device is present.
3 . The power semiconductor module according to claim 1 ,
wherein the second group of at least one power semiconductor device is electrically separated from the members of the first group of power semiconductor devices such that the at least one damaged power semiconductor device is left out of a commutation loop or a commutation cell, respectively, of the power semiconductor module.
4 . The power semiconductor module according to claim 1 , wherein the power semiconductor devices are wide bandgap semiconductor power devices, in particular insulated-gate bipolar transistors, IGBTs, silicon carbide metal-oxide-semiconductor field-effect transistors, SiC MOSFETs, or gallium nitride high-electron-mobility transistors, GAN HEMTs.
5 . The power semiconductor module according to claim 1 , wherein the first group of power semiconductor devices form part of a half-bridge configuration of SiC devices.
6 . The power semiconductor of claim 1 , wherein the power semiconductor is part of an electrical converter.
7 . A method for manufacturing a power semiconductor module, wherein the power semiconductor module comprises a plurality of power semiconductor devices, said method comprising:
a) providing at least one substrate for carrying the plurality of power semiconductor devices; and
b) placing the plurality of power semiconductor devices on the at least one substrate;
wherein, the method further comprises manufacturing steps as follows:
c) determining, if one or more power semiconductor devices of the plurality of power semiconductor devices are damaged;
d) electrically interconnecting at least a part of the power semiconductor devices comprising at least two power semiconductor devices in a parallel configuration;
wherein, after realizing the steps e) and d) and in case of at least one power semiconductor device interconnected in a parallel configuration being a damaged power semiconductor device, electrically separating the at least one damaged power semiconductor device from non-damaged power semiconductor devices such that not all electrical connections between the at least one damaged power semiconductor device and the non-damaged power semiconductor devices are removed; and
wherein, after realizing the steps c) and d), at least two of the electrically interconnected power semiconductor devices in the parallel configuration are non-damaged power semiconductor devices and at least one power semiconductor device which is provided with a measuring arrangement, wherein the measuring arrangement comprises at least one measuring point for measuring at least one of electronic, magnetic and temperature properties of the at least one power semiconductor device, the at least one measuring point being formed by a pre-determined breaking point corresponding to a position of an electrical interconnection structure having a reduced thickness and/or width.
8 . The method according to claim 7 , wherein the steps c) and d) are repetitively performed in turns multiple times, each time for at least one power semiconductor device of the plurality of power semiconductor devices, each time further comprising:
electrically interconnecting a gate contact of a first power semiconductor device,
subsequently, determining whether said first power semiconductor device is damaged, and,
in case of determining that the first power semiconductor device is damaged, disconnecting the first power semiconductor device.
9 . The method according to claim 7 , further comprising providing in step c) at least one measuring point on at least one of the power semiconductor devices for measuring at least one of an electric, magnetic or temperature parameter in order to detect at least one of a gate-emitter leakage, a collector-emitter leakage, a short circuit or an open circuit in the damaged power semiconductor devices during assembly.