POWER SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A POWER SEMICONDUCTOR DEVICE

1 . A power semiconductor device, comprising

a drift layer of a first conductivity type,

at least two well regions of a second conductivity type being different from the first conductivity type,

at least one intermediate region,

a gate provided on the at least one intermediate region, and

a back metal layer provided on the drift layer at a second side opposite a first side of the power semiconductor device, wherein

the at least two well regions and the at least one intermediate region are provided at the first side of the power semiconductor device,

the at least one intermediate region is provided between two of the at least two well regions,

the at least one intermediate region comprises at least one first doped region of the first conductivity type and at least one second doped region of the second conductivity type, and

the at least one first doped region and the at least one second doped region are spaced apart in lateral directions to the at least two well regions.

2 . The power semiconductor device according to claim 1 , wherein

the at least one intermediate region extends along a main extension direction, and

the at least one first doped region and the at least one second doped region are provided consecutively along the main extension direction.

3 . The power semiconductor device according to claim 1 , wherein a maximum doping concentration of at least one of the at least one first doped region or the at least one second doped region is at least two times or at least five times higher than a maximum doping concentration of the drift layer.

4 . The power semiconductor device according to claim 1 , wherein the maximum doping concentration of at least one of the at least one first doped region or the at least one second doped region is at least 1·10 14 cm −3 and at most 1·10 18 cm −3 .

5 . The power semiconductor device according to claim 1 , wherein a width of at least one of the at least one first doped region or the at least one second doped region is at least 0.5 μm and at most 5 μm.

6 . The power semiconductor device according to claim 1 , wherein a length of at least one of the at least one first doped region or the at least one second doped region is at least 0.5 μm and at most 1.5 μm.

7 . The power semiconductor device according to claim 1 , wherein a first depth of the at least two well regions is at most as large as a second depth of the at least one first doped region and as a third depth of the at least one second doped region.

8 . The power semiconductor device according to claim 7 , wherein at least one of the second depth or the third depth are at least 50 nm and at most 1.5 μm.

9 . The power semiconductor device according to claim 2 , wherein a plurality of first doped regions and a plurality of second doped regions are arranged consecutively alternating along the main extension direction.

10 . The power semiconductor device according to claim 1 , further comprising

at least two source regions of the first conductivity type, wherein

at least one of the at least two source regions is provided on each of the at least two well regions.

11 . The power semiconductor device according to claim 10 , wherein the gate overlaps with the at least two source regions at least in places in lateral direction.

12 . Method for producing a power semiconductor device comprising

providing a drift layer of a first conductivity type,

producing at least two well regions of a second conductivity type being different from the first conductivity type at a first side of the drift layer by a doping process,

producing at least one intermediate region at the first side of the drift layer by a further doping process,

providing a gate on the at least one intermediate region, and

providing a back metal layer on the drift layer at a second side of the drift layer opposite the first side, wherein

the at least one intermediate region is produced between two of the at least two well regions,

the at least one intermediate region comprises at least one first doped region of the first conductivity type and at least one second doped region of the second conductivity type,

the at least one first doped region and the at least one second doped region are spaced apart in lateral directions to the at least two well regions.