Granted Patent B2

US 12,417,097 · App. 18/287,193 · Granted Sep 16, 2025

Inventors: Tomoya Yokono (Musashino, JP); Yoshiro Yamabe (Musashino, JP); Teruaki Ishizaki (Musashino, JP)

Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION

G06F9/28G06F9/3001G06F9/30043G06F2209/509

Abstract

Claims (40)

1. An accelerator control system comprising an accelerator control device and an accelerator,

wherein the accelerator control device includes:

first processing circuitry configured to:

store control data including a location of data which is an arithmetic processing target and information specifying content of arithmetic processing of the accelerator; and

determine completion of the arithmetic processing by the accelerator when the control data which has been subjected to the arithmetic processing by the accelerator is stored in a storage, and

the accelerator includes:

second processing circuitry configured to:

acquire the control data from the storage;

perform arithmetic processing on the data which is an arithmetic processing target according to the location of the data which is an arithmetic processing target and information specifying an operation of the accelerator included in the acquired control data; and

store the control data in the storage when the arithmetic processing performed by the second processing circuitry is completed.

2. The accelerator control system according to claim 1 , wherein the second processing circuitry is further configured to monitor whether or not the control data is present in the storage.

3. The accelerator control system according to claim 1 , wherein the first processing circuitry is further configured to monitor whether or not the control data which has been subjected to the arithmetic processing by the second processing circuitry is present in the storage.

4. The accelerator control system according to claim 1 , wherein the second processing circuitry is further configured to store, in the storage, a result of the arithmetic processing performed on the data by the second processing circuitry which is an arithmetic processing target.

5. The accelerator control system according to claim 1 , wherein the first processing circuitry is further configured to store control data different for each of a plurality of accelerators.

6. An accelerator control method, comprising:

acquiring control data, the control data including a location of data which is an arithmetic processing target and information specifying content of arithmetic processing of an accelerator;

performing arithmetic processing on the data which is an arithmetic processing target according to the location of the data which is an arithmetic processing target and information specifying an operation of the accelerator included in the acquired control data;

storing the control data when the arithmetic processing is completed; and

determining completion of the arithmetic processing when the control data which has been subjected to the arithmetic processing is stored.

7. A non-transitory computer-readable recording medium storing therein an accelerator control program that causes a computer to execute a process comprising:

acquiring control data including a location of data which is an arithmetic processing target and information specifying content of arithmetic processing of the accelerator;

performing arithmetic processing on the data which is an arithmetic processing target according to the location of the data which is an arithmetic processing target and information specifying an operation of the accelerator included in the acquired control data;

storing the control data when the arithmetic processing is completed; and

determining completion of the arithmetic processing when the control data which has been subjected to the arithmetic processing is stored.

8. The accelerator control method according to claim 6 , further comprising:

monitoring whether or not the control data has been stored.

9. The accelerator control method according to claim 6 , further comprising:

monitoring whether or not the control data which has been subjected to the arithmetic processing has been stored.

10. The accelerator control method according to claim 6 , further comprising:

storing a result of the arithmetic processing performed on the data which is an arithmetic processing target.

11. The accelerator control method according to claim 6 , further comprising:

storing control data which is different for each of a plurality of accelerators.

12. The non-transitory computer-readable recording medium according to claim 7 , wherein the processing further comprises:

monitoring whether or not the control data has been stored.

13. The non-transitory computer-readable recording medium according to claim 7 , wherein the processing further comprises:

monitoring whether or not the control data which has been subjected to the arithmetic processing has been stored.

14. The non-transitory computer-readable recording medium according to claim 7 , wherein the processing further comprises:

storing a result of the arithmetic processing performed on the data which is an arithmetic processing target.

15. The non-transitory computer-readable recording medium according to claim 7 , wherein the processing further comprises:

storing control data which is different for each of a plurality of accelerators.

Assignments (2)

Continuity (1)

References Cited (12)