SYSTEMS AND METHODS FOR QUANTUM COMPUTING USING FLUXONIUM QUBITS WITH KINETIC INDUCTORS
A superconducting device may have a body loop comprising a body loop comprising a Josephson junction structure and a kinetic inductor. The superconducting device can be a qubit in a quantum processor for performing gate-model quantum computation. The superconducting device may be fabricated with a single wiring layer embedded in a single-crystalline substrate trench. The superconducting device may be fabricated with a wiring layer and an insulating layer in a single-crystalline substrate trench. The superconducting device may be fabricated with multiple wiring layers embedded in a single-crystalline substrate trench. The device may be fabricated by defining trenches in the single-crystalline substrate, with the trenches having a depth matching the desired numbers of wiring layers and insulating layers.
1 . A superconducting device comprising:
a body loop comprising:
a Josephson junction structure comprising at least one inductor in series with at least one Josephson junction; and
a kinetic inductor, the kinetic inductor comprising a segment of kinetic inductance material.
2 . The superconducting device of claim 1 , wherein the body loop has a body loop material comprising at least one of Al and Nb.
3 . The superconducting device of claim 1 wherein the Josephson junction structure comprises a compound Josephson junction, each Josephson junction in the compound Josephson junction in series with a respective inductor.
4 . The superconducting device of claim 1 , wherein the segment of kinetic inductance material comprises at least one of NbN, NbTiN, TiN, AlN and granular Aluminum.
5 . The superconducting device of claim 1 , wherein the kinetic inductor is embedded into a first layer and the Josephson junction structure is embedded into a second layer, the second layer separate from the first layer.
6 . The superconducting device of claim 5 , wherein the first layer is adjacent to a high-resistivity layer.
7 . The superconducting device of claim 5 , wherein the first layer is interposed within a high-resistivity layer.
8 . The superconducting device of claim 6 or 7 , wherein the high-resistivity layer is a single-crystalline substrate layer.
9 . The superconducting device of claim 8 , wherein the single-crystalline substrate layer is selected from a group comprising: c-Silicon and Sapphire.
10 . The superconducting device of claim 7 , further comprising an insulating layer interposed within the high-resistivity layer.
11 . The superconducting device of claim 10 , further comprising a plurality of wiring layers interposed within the high-resistivity layer.
12 . The superconducting device of claim 5 , wherein the first and the second layer are separated by at least one insulating dielectric layer.
13 . The superconducting device of claim 5 , wherein the first and the second layer are separated by N dielectric-wiring layer pairs.
14 . The superconducting device of claim 13 , wherein at least one of the N dielectric-wiring layer pairs comprises a Al.
15 . A processor comprising a plurality of superconducting devices, each superconducting device comprising:
a body loop comprising:
a Josephson junction structure comprising at least one inductor in series with at least one Josephson junction; and
a kinetic inductor, the kinetic inductor comprising a segment of kinetic inductance material.
16 . The processor of claim 15 , wherein the body loop has a body loop material comprising at least one of Al and Nb.
17 . The processor of claim 15 , wherein the Josephson junction structure comprises a compound Josephson junction, each Josephson junction in the compound Josephson junction in series with a respective inductor.
18 . The processor of claim 15 , wherein the segment of kinetic inductance material comprises at least one of NbN, NbTiN, TiN, AlN, and granular Aluminum.
19 . The processor of claim 15 , wherein the kinetic inductor is embedded into a first layer and the Josephson junction structure is embedded into a second layer, the second layer separate from the first layer.
20 . The processor of claim 19 , wherein the first layer is adjacent to a high-resistivity layer.
21 . The processor of claim 19 , wherein the first layer is interposed within the high-resistivity layer.
22 . The processor of claim 20 or 21 , wherein the high-resistivity layer is a single-crystalline substrate layer.
23 . The processor of claim 22 , wherein the single-crystalline substrate layer is selected from a group comprising: c-Silicon and Sapphire.
24 . The processor of claim 21 , further comprising an insulating layer interposed within the high-resistivity layer.
25 . The processor of claim 24 , further comprising a plurality of wiring layers interposed within the high-resistivity layer.
26 . The processor of claim 19 , wherein the first and the second layer are separated by at least one insulating dielectric layer.
27 . The processor of claim 19 , wherein the first and the second layer are separated by N dielectric-wiring layer pairs.
28 . The processor of claim 27 , wherein at least one of the N dielectric-wire layer pairs comprises Al.
29 . The processor of claim 15 , wherein each superconducting device in the plurality of superconducting devices is a qubit.
30 . The processor of claim 29 , wherein the plurality of qubits is operable to perform gate-model quantum computation.
31 . A method of fabrication of a superconducting device, the method comprising:
providing a high-resistivity layer;
defining trenches in the high-resistivity layer;
depositing a first superconducting wiring layer to overlie at least a portion of the high-resistivity layer and within the trenches, wherein the first superconducting wiring layer comprises material that is superconducting in a range of critical temperatures; and
removing a portion of the first superconducting wiring layer from the high-resistivity layer to define the first superconducting wiring layer within the trenches.
32 . The method of claim 31 , wherein depositing a high-resistivity layer includes depositing a single-crystalline substrate layer.
33 . The method of claim 31 , wherein depositing a single-crystalline substrate layer includes depositing a single-crystalline substrate selected from a group comprising: c_Silicon and Sapphire.
34 . The method of claim 31 , further comprising removing oxide from the high-resistivity layer before depositing a first superconducting wiring layer.
35 . The method of claim 34 , wherein removing oxide from the high-resistivity layer includes removing oxide from the high-resistivity layer using a Hydrofluoric acid (HF) dip.
36 . The method of claim 31 , wherein defining trenches in the high-resistivity layer includes forming trenches in the high-resistivity layer having a depth that matches a depth of the first superconducting wiring layer in all places where the first superconducting wiring layer will be defined.
37 . The method of claim 31 , wherein depositing a first superconducting wiring layer includes deposing a material selected from a group comprising Nb, Al, and Ta.
38 . The method of claim 31 , wherein depositing a first superconducting wiring layer includes deposing a segment of kinetic inductor material.
39 . The method of claim 38 , wherein deposing a segment of kinetic inductor material includes depositing a segment of material selected from a group comprising NbN, NbTiN, TiN, AlN, and granular Aluminum.
40 . The method of claim 31 , wherein removing a portion of the first superconducting wiring layer from the high-resistivity layer includes polishing off a portion of the first superconducting wiring layer using chemo-mechanical polishing (CMP).
41 . A method of fabrication of a superconducting device, the method comprising:
providing a high-resistivity layer;
defining trenches in the high-resistivity layer;
depositing a first superconducting wiring layer to overlie at least a portion of the high-resistivity layer and within the trenches, wherein the first superconducting wiring layer comprises material that is superconducting in a range of critical temperatures;
removing a first portion of the first superconducting wiring layer from the high-resistivity layer to define the first superconducting wiring layer within the trenches;
defining a photoresist over a first region of the first superconducting wiring layer within the trenches;
removing a second portion of the first superconducting wiring layer to define studs for vias;
depositing a dielectric layer to overlie the first superconducting wiring layer; and
removing a first portion of the dielectric layer to define the dielectric layer within the trenches.
42 . The method of claim 41 , wherein providing a high-resistivity layer includes providing a single-crystalline substrate layer.
43 . The method of claim 42 , wherein providing a single-crystalline substrate layer includes providing a single-crystalline substrate selected from a group comprising: c-Silicon and Sapphire.
44 . The method of claim 41 , further comprising removing oxide from the high-resistivity layer before depositing a first superconducting wiring layer.
45 . The method of claim 44 , wherein removing oxide from the high-resistivity layer includes removing oxide from the high-resistivity layer using a Hydrofluoric acid (HF) dip.
46 . The method of claim 41 , wherein defining trenches in the high-resistivity layer includes forming trenches having a depth that at least approximately matches a height of the first superconducting wiring layer plus a height of the dielectric layer in the high-resistivity layer in all places where the first superconducting wiring layer will be defined.
47 . The method of claim 41 , wherein depositing a first superconducting wiring layer to overlie at least a portion of the high-resistivity layer and within the trenches includes depositing a first superconducting wiring layer to overlie at least a portion of the high-resistivity layer to fill the trenches.
48 . The method of claim 41 , wherein depositing a first superconducting wiring layer includes deposing a material selected from a group comprising Nb, Al, and Ta.
49 . The method of claim 41 , wherein depositing a first superconducting wiring layer includes deposing a segment of kinetic inductor material.
50 . The method of claim 49 , wherein deposing a segment of kinetic inductor material includes depositing a segment of material selected from a group comprising NbN, NbTiN, TiN, AlN, and granular Aluminum.
51 . The method of claim 41 , wherein removing a first portion of the first superconducting wiring layer includes polishing off a first portion of the first superconducting wiring layer using chemo-mechanical polishing (CMP).
52 . The method of claim 41 , wherein defining a photoresist over a first region of the first superconducting wiring layer within the trenches includes defining a photoresist over a first region of the first superconducting wiring layer within the trenches, the first region comprising studs for vias.
53 . The method of claim 41 , wherein removing a second portion of the first superconducting wiring layer includes etching a second portion of the first superconducting wiring layer.
54 . The method of claim 41 , wherein depositing a dielectric layer to overlie the first superconducting wiring layer includes depositing a dielectric layer to overlie the first superconducting wiring layer to fill the trenches.
55 . The method of claim 41 , wherein removing a first portion of the dielectric layer includes polishing off a first portion of the dielectric layer using CMP.
56 . A method of fabrication of a superconducting device, the method comprising:
providing a high-resistivity layer;
defining trenches in the high-resistivity layer;
until i=N and j=N, where N>1, repeating:
depositing an i th superconducting wiring layer to overlie at least a portion of the high-resistivity layer and within the trenches, wherein the i th superconducting wiring layer comprises material that is superconducting in a range of critical temperatures;
removing a respective first portion of the i th superconducting wiring layer from the high-resistivity layer to define the i th superconducting wiring layer within the trenches;
defining a photoresist over a respective first region of the i th superconducting wiring layer within the trenches;
removing a respective second portion of the i th superconducting wiring layer to define studs for vias;
depositing a j th dielectric layer to overlie the i th superconducting wiring layer;
removing a respective first portion of the j th dielectric layer to define the j th dielectric layer in the trenches;
defining a photoresist over a respective first region of the j th dielectric layer within the trenches; and
removing a respective second portion of the j th dielectric layer.
57 . The method of claim 56 , wherein providing a high-resistivity layer includes providing a single-crystalline substrate layer.
58 . The method of claim 57 , wherein providing a single-crystalline substrate includes providing a single-crystalline substrate selected from a group comprising: c-Silicon and Sapphire.
59 . The method of claim 56 , wherein removing oxide from the high-resistivity layer includes removing oxide from the high-resistivity layer using an Hydrofluoric acid (HF) dip.
60 . The method of claim 56 , wherein defining trenches in the high-resistivity layer includes forming trenches having a depth equal to a height of N superconducting wiring layers plus a height of N dielectric layers in the high-resistivity layer in all places where the N superconducting wiring layers will be defined.
61 . The method of claim 56 , wherein depositing an i th superconducting wiring layer includes deposing a material selected from a group comprising Nb, Al, and Ta.
62 . The method of claim 56 , wherein depositing an i th superconducting wiring layer includes deposing a segment of kinetic inductor material.
63 . The method of claim 62 , wherein deposing a segment of kinetic inductor material includes depositing a segment of material selected from a group comprising NbN, NbTiN, TiN, AlN, and granular Aluminum.
64 . The method of claim 56 , wherein depositing an i th superconducting wiring layer includes depositing the i th superconducting wiring layer to completely fill the trenches.
65 . The method of claim 56 , wherein removing a respective first portion of the i th superconducting wiring layer includes polishing off a respective first portion of the i th superconducting wiring layer using CMP.
66 . The method of claim 56 , wherein defining a photoresist over a respective first region of the i th superconducting wiring layer within the trenches includes defining a photoresist over a respective first region of the i th superconducting wiring layer within the trenches, the first region comprising studs for vias.
67 . The method of claim 56 , wherein removing a respective second portion of the i th superconducting wiring layer includes etching a respective second portion of the i th superconducting wiring layer.
68 . The method of claim 56 , wherein depositing a j th dielectric layer to overlie the i th superconducting wiring layer includes depositing a j th dielectric layer to overlie the i th superconducting wiring layer to completely fill the trenches.
69 . The method of claim 56 , wherein removing a respective first portion of the j th dielectric layer includes removing a respective first portion of the j th dielectric layer using CMP.
70 . The method of claim 56 , wherein defining a photoresist over a respective first region of the j th dielectric layer within the trenches includes defining a photoresist over a respective first region of the j th dielectric layer within the trenches, the first region comprising studs for vias.
71 . The method of claim 56 , wherein removing a respective second portion of the j th dielectric layer includes etching a respective second portion of the j th dielectric layer.
72 . The method of claim 56 , further comprising removing oxide from the high-resistivity layer before defining trenches in the high-resistivity layer.