Fixed-size image alpha channel compression techniques
A system and method for fixed size texture compression utilizing dynamic alpha channel compression utilizes block-based compression. The method includes determining a first endpoint of a pixel block including four pixels, each pixel represented by a plurality of channels; determining a second endpoint of the pixel block, which is not the first endpoint; encoding the first endpoint and the second endpoint using a first plurality of bits; encoding a first quantization level using a second plurality of bits; encoding a second quantization level using a third plurality of bits; encoding an alpha map of the four pixels using a fourth plurality of bits; encoding a location of the first endpoint and a location of the second endpoint using a fifth plurality of bits; and storing an addressing indicator bit based on a distance between a value of the first endpoint and a value of the second endpoint.
1. A method for fixed size texture compression utilizing dynamic alpha channel compression, comprising:
determining a first endpoint of a pixel block including four pixels, each pixel represented by a plurality of channels;
determining a second endpoint of the pixel block, which is not the first endpoint;
encoding the first endpoint and the second endpoint using a first plurality of bits;
encoding a first quantization level using a second plurality of bits;
encoding a second quantization level using a third plurality of bits;
detecting a number of visible pixels;
encoding an alpha map of the four pixels using a first portion of a fourth plurality of bits, wherein the first portion of the fourth plurality of bits is configured to store a value which corresponds to one of twelve alpha maps, each alpha map distinct from another alpha map;
encoding an average alpha value using a second portion of the fourth plurality of bits;
encoding a location of the first endpoint and a location of the second endpoint using a fifth plurality of bits; and
storing an addressing indicator bit based on a distance between a value of the first endpoint and a value of the second endpoint.
2. The method of claim 1 , wherein the first portion of the fourth plurality of bits is 4 bits, and the fourth plurality of bits is 8 bits.
3. The method of claim 1 , further comprising:
detecting that all four pixels are visible; and
encoding an alpha indicator using a third portion of the fourth plurality of bits; and
encoding an average alpha value using a fourth portion of the fourth plurality of bits, which is larger than the second portion of the fourth plurality of bits.
4. The method of claim 3 , wherein the fourth portion of the fourth plurality of bits is 6 bits.
5. The method of claim 1 , further comprising:
storing the first endpoint utilizing a first encoding in response to determining that the addressing indicator bit has a first binary value.
6. The method of claim 5 , further comprising:
storing the first endpoint utilizing a second encoding in response to determining that the addressing indicator bit has a second binary value.
7. The method of claim 1 , wherein the first endpoint and the second endpoint are encoded using a total of 31 bits.
8. The method of claim 1 , further comprising:
determining a visibility threshold for the pixel block; and
selecting the alpha map based on the visibility threshold.
9. A non-transitory computer readable medium having stored thereon instructions for causing a processing circuitry to execute a process, the process comprising:
determining a first endpoint of a pixel block including four pixels, each pixel represented by a plurality of channels;
determining a second endpoint of the pixel block, which is not the first endpoint;
encoding the first endpoint and the second endpoint using a first plurality of bits;
encoding a first quantization level using a second plurality of bits;
encoding a second quantization level using a third plurality of bits;
detecting a number of visible pixels;
encoding an alpha map of the four pixels using a first portion of a fourth plurality of bits, wherein the first portion of the fourth plurality of bits is configured to store a value which corresponds to one of twelve alpha maps, each alpha map distinct from another alpha map;
encoding an average alpha value using a second portion of the fourth plurality of bits;
encoding a location of the first endpoint and a location of the second endpoint using a fifth plurality of bits; and
storing an addressing indicator bit based on a distance between a value of the first endpoint and a value of the second endpoint.
10. A system for fixed size texture compression utilizing dynamic alpha channel compression, comprising:
a processing circuitry; and
a memory, the memory containing instructions that, when executed by the processing circuitry, configure the system to:
determine a first endpoint of a pixel block including four pixels, each pixel represented by a plurality of channels;
determine a second endpoint of the pixel block, which is not the first endpoint;
encode the first endpoint and the second endpoint using a first plurality of bits;
encode a first quantization level using a second plurality of bits;
encode a second quantization level using a third plurality of bits;
detect a number of visible pixels;
encode an alpha map of the four pixels using a first portion of a fourth plurality of bits, wherein the first portion of the fourth plurality of bits is configured to store a value which corresponds to one of twelve alpha maps, each alpha map distinct from another alpha map;
encode an average alpha value using a second portion of the fourth plurality of bits;
encode a location of the first endpoint and a location of the second endpoint using a fifth plurality of bits; and
store an addressing indicator bit based on a distance between a value of the first endpoint and a value of the second endpoint.
11. The system of claim 10 , wherein the first portion of the fourth plurality of bits is 4 bits, and the fourth plurality of bits is 8 bits.
12. The system of claim 10 , further comprising:
detecting that all four pixels are visible; and
encoding an alpha indicator using a third portion of the fourth plurality of bits; and
encoding an average alpha value using a fourth portion of the fourth plurality of bits, which is larger than the second portion of the fourth plurality of bits.
13. The system of claim 12 , wherein the fourth portion of the fourth plurality of bits is 6 bits.
14. The system of claim 10 , further comprising:
storing the first endpoint utilizing a first encoding in response to determining that the addressing indicator bit has a first binary value.
15. The system of claim 14 , further comprising:
storing the first endpoint utilizing a second encoding in response to determining that the addressing indicator bit has a second binary value.
16. The system of claim 10 , wherein the first endpoint and the second endpoint are encoded using a total of 31 bits.
17. The system of claim 10 , further comprising:
determining a visibility threshold for the pixel block; and
selecting the alpha map based on the visibility threshold.