Fixed-size block compression techniques for RGB channels
A system and method for fixed size texture compression utilizes a four pixel block. The method includes determining a first endpoint of a pixel block including four pixels, each pixel represented by a red channel, a green channel and a blue channel; determining a second endpoint of the pixel block, which is not the first endpoint; encoding the first endpoint and the second endpoint using a first plurality of bits; encoding a first quantization level using a second plurality of bits; encoding a second quantization level using a third plurality of bits; encoding a location of the first endpoint and a location of the second endpoint using a fourth plurality of bits; and encoding an addressing indicator bit based on a distance between a value of the first endpoint and a value of the second endpoint.
1 . A method for fixed size texture compression, comprising:
determining a first endpoint of a pixel block including four pixels, each pixel represented by a red channel, a green channel and a blue channel, wherein the first endpoint is a pixel of the pixel block;
determining a second endpoint of the pixel block, which is not the first endpoint, wherein the second endpoint is another pixel of the pixel block;
encoding the first endpoint and the second endpoint using a first plurality of bits;
encoding a first quantization level using a second plurality of bits;
encoding a second quantization level using a third plurality of bits;
encoding a location of the first endpoint and a location of the second endpoint using a fourth plurality of bits; and
encoding an addressing indicator bit based on a distance between a value of the first endpoint and a value of the second endpoint.
2 . The method of claim 1 , further comprising:
storing the first endpoint utilizing a first encoding of nineteen bits and storing the second endpoint utilizing a second encoding of nineteen bits in response to determining that the addressing indicator bit has a first binary value.
3 . The method of claim 2 , wherein the first encoding represents a red channel with 6 bits, a green channel with 7 bits, and a blue channel with 6 bits.
4 . The method of claim 2 , wherein the second encoding represents a red channel with 6 bits, a green channel with 7 bits, and a blue channel with 6 bits.
5 . The method of claim 1 , further comprising:
storing the first endpoint utilizing twenty four bits and storing the second endpoint utilizing a third encoding of fourteen bits in response to determining that the addressing indicator bit has a second binary value.
6 . The method of claim 5 , wherein the third encoding represents an offset from a green channel of the first endpoint with 5 bits.
7 . The method of claim 5 , wherein the third encoding further represents an offset from the red channel of the first endpoint with 5 bits.
8 . The method of claim 1 , further comprising:
encoding the first endpoint using 24 bits; and
encoding the second endpoint such that each value of a channel of the second endpoint is encoded relative to a value of a corresponding channel of the first endpoint.
9 . The method of claim 1 , further comprising:
encoding a green channel of the first endpoint using a first portion of the first plurality of bits;
encoding a red channel of the first endpoint using a second portion of the first plurality of bits; and
encoding a blue channel of the first endpoint using a third portion of the first plurality of bits, wherein a number of bits of the first portion is greater than a number of bits of each of the second portion and the third portion.
10 . A non-transitory computer readable medium having stored thereon instructions for causing a processing circuitry to execute a process, the process comprising:
determining a first endpoint of a pixel block including four pixels, each pixel represented by a red channel, a green channel and a blue channel, wherein the first endpoint is a pixel of the pixel block;
determining a second endpoint of the pixel block, which is not the first endpoint, wherein the second endpoint is another pixel of the pixel block;
encoding the first endpoint and the second endpoint using a first plurality of bits;
encoding a first quantization level using a second plurality of bits;
encoding a second quantization level using a third plurality of bits;
encoding a location of the first endpoint and a location of the second endpoint using a fourth plurality of bits; and
encoding an addressing indicator bit based on a distance between a value of the first endpoint and a value of the second endpoint.
11 . A system for fixed size texture compression, comprising:
a processing circuitry; and
a memory, the memory containing instructions that, when executed by the processing circuitry, configure the system to:
determine a first endpoint of a pixel block including four pixels, each pixel represented by a red channel, a green channel and a blue channel, wherein the first endpoint is a pixel of the pixel block;
determine a second endpoint of the pixel block, which is not the first endpoint, wherein the second endpoint is another pixel of the pixel block;
encode the first endpoint and the second endpoint using a first plurality of bits;
encode a first quantization level using a second plurality of bits;
encode a second quantization level using a third plurality of bits;
encode a location of the first endpoint and a location of the second endpoint using a fourth plurality of bits; and
encode an addressing indicator bit based on a distance between a value of the first endpoint and a value of the second endpoint.
12 . The system of claim 11 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
store the first endpoint utilizing a first encoding of nineteen bits and storing the second endpoint utilizing a second encoding of nineteen bits in response to determining that the addressing indicator bit has a first binary value.
13 . The system of claim 12 , wherein the first encoding represents a red channel with 6 bits, a green channel with 7 bits, and a blue channel with 6 bits.
14 . The system of claim 12 , wherein the second encoding represents a red channel with 6 bits, a green channel with 7 bits, and a blue channel with 6 bits.
15 . The system of claim 11 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
store the first endpoint utilizing twenty four bits and storing the second endpoint utilizing a third encoding of fourteen bits in response to determining that the addressing indicator bit has a second binary value.
16 . The system of claim 15 , wherein the third encoding represents an offset from a green channel of the first endpoint with 5 bits.
17 . The system of claim 15 , wherein the third encoding further represents an offset from the red channel of the first endpoint with 5 bits.
18 . The system of claim 11 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
encode the first endpoint using 24 bits; and
encode the second endpoint such that each value of a channel of the second endpoint is encoded relative to a value of a corresponding channel of the first endpoint.
19 . The system of claim 11 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
encode a green channel of the first endpoint using a first portion of the first plurality of bits;
encode a red channel of the first endpoint using a second portion of the first plurality of bits; and
encode a blue channel of the first endpoint using a third portion of the first plurality of bits, wherein a number of bits of the first portion is greater than a number of bits of each of the second portion and the third portion.