IP Library Granted Patent US 12,620,942
Granted Patent B2
US 12,620,942 · App. 18/307,494 · Granted May 5, 2026

Bias circuit for stacked power amplifiers with a variable power supply

Inventors: Shota Ishihara (San Diego, CA); Rui Ma (Carlisle, MA)
Assignee: Murata Manufacturing Co., Ltd.
H03F1/301H03F1/56H03F3/211H03F2200/21H03F2200/222H03F2200/387H03F2200/451
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Quick Facts
Patent No.
US 12,620,942
App. No.
18/307,494
Granted
May 5, 2026
Kind
B2
Abstract

Stacked amplifier architectures that have bias circuits that are tolerant of supply voltage variations, which provide good reliability, are fast to follow V CC changes, and exhibit small variations in gain as V CC varies. One embodiment encompasses a bias circuit for an amplifier stack, including a source follower circuit configured to output a bias voltage to a transistor within the amplifier stack and configured to be coupled to a variable voltage, and a controller coupled to the source follower circuit, configured to be coupled to a constant voltage, and configured to apply a constant voltage to the source follower circuit. The source follower circuit generates a reference voltage and (1) outputs a constant bias voltage when the variable voltage is above the reference voltage, and (2) outputs a bias voltage proportional to the variable voltage when the variable voltage is below the reference voltage.

Claims (48)

1 . A bias circuit for an amplifier stack configured to be coupled to a variable voltage source, the bias circuit including:

(a) a source follower circuit including an input terminal, an output terminal, and a control input, the source follower circuit configured to output a bias voltage on the output terminal when coupled to a gate of a transistor within the amplifier stack, and configured to have the input terminal be coupled to the variable voltage source for the amplifier stack; and

(b) a controller coupled to the control input of the source follower circuit, configured to be coupled to a constant voltage source, and configured to apply a constant voltage to the control input of the source follower circuit.

2 . The bias circuit of claim 1 , wherein the source follower circuit includes:

(a) a source follower transistor having a conduction channel connected between the input terminal and the output terminal and configured to be coupled through the input terminal to the variable voltage source for the amplifier stack, the source follower transistor having a gate configured as the control input;

(b) a first resistor coupled between the output terminal and a reference potential; and

(c) a node between the output terminal and the resistor, the node configured to be coupled to the gate of the transistor within the amplifier stack.

3 . The bias circuit of claim 2 , wherein the controller includes:

(a) a transistor having a conduction channel configured to be coupled to the constant voltage source and having a gate;

(b) a second resistor coupled to the conduction channel of the transistor;

(c) a third resistor coupled between the second resistor and the reference potential;

(d) an operational amplifier having a first input coupled to a node between the second and third resistors, a second input coupled to a reference voltage, and an output coupled to the gate of the transistor and to the gate of the source follower transistor.

4 . The bias circuit of claim 3 , further including a capacitor coupled to the gate of the source follower transistor.

5 . The bias circuit of claim 2 , wherein the source follower circuit outputs a constant bias voltage when a voltage of the variable voltage source is above a gate reference voltage generated within the controller.

6 . The bias circuit of claim 2 , wherein the source follower circuit outputs a bias voltage proportional to a voltage of the variable voltage source when the voltage of the variable voltage source is below a gate reference voltage generated within the controller.

7 . The bias circuit of claim 2 , wherein the source follower circuit generates a gate reference voltage and (1) outputs a constant bias voltage when a voltage of the variable voltage source is above the gate reference voltage, and (2) outputs a bias voltage proportional to the voltage of the variable voltage source when the voltage of the variable voltage source is below the gate reference voltage.

8 . The bias circuit of claim 2 , wherein the source follower transistor is a MOSFET.

9 . A bias circuit for an amplifier stack, the bias circuit including:

(a) a source follower circuit configured to output a bias voltage when coupled to a gate of a transistor within the amplifier stack, the source follower circuit configured to be coupled to a variable voltage source for the amplifier stack, wherein the source follower circuit includes:

(1) a source follower transistor having a conduction channel configured to be coupled to the variable voltage source and having a gate;

(2) a first resistor coupled between the conduction channel of the source follower transistor and a reference potential; and

(3) an output between the source follower transistor and the resistor, the output configured to be coupled to the gate of the transistor within the amplifier stack; and

(b) a controller coupled to the source follower circuit, configured to be coupled to a constant voltage source, and configured to apply a constant voltage to the source follower circuit, wherein the controller includes:

(1) a transistor having a conduction channel configured to be coupled to the constant voltage source and having a gate;

(2) a second resistor coupled to the conduction channel of the transistor;

(3) a third resistor coupled between the second resistor and the reference potential;

(4) an operational amplifier having a first input coupled to a node between the second and third resistors, a second input coupled to a reference voltage, and an output coupled to the gate of the transistor and to the gate of the source follower transistor.

10 . The bias circuit of claim 9 , further including a capacitor coupled to the gate of the source follower transistor.

11 . An amplifier, including:

(a) an amplifier stack comprising at least two series-connected FETs and configured to be coupled to a variable voltage source;

(b) a bias circuit for the amplifier stack, the bias circuit including, for at least one FET within the amplifier stack:

(1) a source follower circuit including an input terminal, an output terminal coupled to a gate of the at least one FET, and a control input, the source follower circuit configured to have the input terminal be coupled to the variable voltage source for the amplifier stack and to output a bias voltage on the output terminal to the gate of the at least one FET; and

(2) a controller coupled to the control input of the source follower circuit, configured to be coupled to a constant voltage source, and configured to apply a constant voltage to the control input of the source follower circuit.

12 . The amplifier of claim 11 , wherein the source follower circuit includes:

(a) a source follower transistor having a conduction channel connected between the input terminal and the output terminal and configured to be coupled through the input terminal to the variable voltage source for the amplifier stack, the source follower transistor having a gate configured as the control input;

(b) a first resistor coupled between the output terminal and a reference potential; and

(c) a node between the output terminal and the resistor, the node configured to be coupled to the gate of the at least one FET within the amplifier stack.

13 . The amplifier of claim 12 , wherein the controller includes:

(a) a transistor having a conduction channel configured to be coupled to the constant voltage source and having a gate;

(b) a second resistor coupled to the conduction channel of the transistor;

(c) a third resistor coupled between the second resistor and the reference potential;

(d) an operational amplifier having a first input coupled to a node between the second and third resistors, a second input coupled to a reference voltage, and an output coupled to the gate of the transistor and to the gate of the source follower transistor.

14 . The amplifier of claim 13 , further including a capacitor coupled to the gate of the source follower transistor.

15 . The amplifier of claim 11 , wherein the source follower circuit outputs a constant bias voltage when a voltage of the variable voltage source is above a gate reference voltage generated within the controller.

16 . The amplifier of claim 11 , wherein the source follower circuit outputs a bias voltage proportional to a voltage of the variable voltage source when the voltage of the variable voltage source is below a gate reference voltage generated within the controller.

17 . The amplifier of claim 11 , wherein the source follower circuit generates a gate reference voltage and (1) outputs a constant bias voltage when a voltage of the variable voltage source is above the gate reference voltage, and (2) outputs a bias voltage proportional to the voltage of the variable voltage source when the voltage of the variable voltage source is below the gate reference voltage.

18 . The amplifier of claim 11 , wherein the source follower transistor is a MOSFET.

19 . The amplifier of claim 11 , wherein at least one FET within the amplifier stack is coupled to and biased by a resistive ladder bias circuit.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2024
From: PSEMI CORPORATION
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 066597/0427 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 17, 2023
From: ISHIHARA, SHOTA; MA, RUI
To: PSEMI CORPORATION
Reel/Frame 064287/0786 →
Continuity (1)
Related Publication 20240364274A1 · Oct 31, 2024
References Cited (12)
US 4929907A · Berkel · 1990 [cited by applicant]
US 9543901B2 · Nobbe et al. · 2017 [cited by applicant]
US 9768743B1 · Tam et al. · 2017 [cited by applicant]
US 9843293B1 · Wagh · 2017 [cited by examiner]
US 10756678B2 · Klaren · 2020 [cited by examiner]
US 11128261B2 · Ranta et al. · 2021 [cited by applicant]
US 11601094B2 · Klaren et al. · 2023 [cited by applicant]
US 20160126901A1 · Knopik · 2016 [cited by applicant]
US 20190158029A1 · Wagh et al. · 2019 [cited by applicant]
US 20190190459A1 · Wagh · 2019 [cited by examiner]
US 20200127622A1 · Matsumoto · 2020 [cited by examiner]
Dubret, Francoise, International Search Report and Written Opinion received from the EPO dated Jul. 24, 24 for appln. No. PCT/JP2024/016173, 18 pgs. [cited by applicant]