Synthesis driven for minimum leakage with new standard cells

1. An integrated circuit, comprising:

a complementary metal-oxide-semiconductor (CMOS) logic gate including a first p-channel transistor and a first n-channel transistor, wherein the first p-channel transistor is configurable to be body biased;

a series p-channel transistor coupled between an output terminal of the CMOS logic gate and the first p-channel transistor, wherein the series p-channel transistor is configurable to be body biased; and

a shunt n-channel transistor coupled between the output terminal of the CMOS logic gate and reference ground, wherein a gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low-power operating mode of the CMOS logic gate.

2. The integrated circuit of claim 1 , wherein the first p-channel transistor and the series p-channel transistor are coupled in series between a voltage source terminal of the CMOS logic gate and the output terminal of the CMOS logic gate, and wherein the first n-channel transistor and the shunt n-channel transistor are coupled in parallel between the output terminal of the CMOS logic gate and the reference ground.

3. The integrated circuit of claim 1 , wherein a body bias voltage is applied to the first p-channel transistor and the series p-channel transistor to body bias the first p-channel transistor and the series p-channel transistor.

4. The integrated circuit of claim 1 , wherein the CMOS logic gate includes a second p-channel transistor and a second n-channel transistor, wherein the second p-channel transistor is configurable to be body biased, wherein the first p-channel transistor, the second p-channel transistor, and the series p-channel transistor are arranged in series between a voltage source terminal of the CMOS logic gate and the output terminal of the CMOS logic gate, and wherein the first n-channel transistor, the second n-channel transistor, and the shunt n-channel transistor are coupled in parallel between the output terminal of the CMOS logic gate and the reference ground.

5. The integrated circuit of claim 1 , wherein the CMOS logic gate includes a second p-channel transistor and a second n-channel transistor, wherein the second p-channel transistor is configurable to be body biased, wherein the first p-channel transistor and the second p-channel transistor are arranged in parallel between a voltage source terminal of the CMOS logic gate and the series p-channel transistor, and wherein the first n-channel transistor, the second n-channel transistor, and the shunt n-channel transistor are coupled in parallel between the output terminal of the CMOS logic gate and the reference ground.

6. The integrated circuit of claim 1 , wherein the CMOS logic gate is a logic NAND gate, a logic NOR gate, a logic NOT gate, or a combination thereof.

7. The integrated circuit of claim 1 , further comprising a multiplexer having a first input terminal, a second input terminal, a select terminal, and an output terminal, wherein the first input terminal is coupled to the output terminal of the CMOS logic gate, wherein the second input terminal is couplable to a controller, wherein the select terminal is coupled to the sleep signal, and wherein the multiplexer is configured to:

set an output signal at the output terminal of the multiplexer to a signal at the first input terminal in response to the sleep signal being de-asserted; and

set an output signal at the output terminal of the multiplexer to a signal at the second input terminal in response to the sleep signal being asserted, wherein the signal at the second input terminal is a desired output value.

8. A complementary metal-oxide-semiconductor (CMOS) logic gate, comprising:

a first p-channel transistor coupled between a voltage source terminal of the CMOS logic gate and an output terminal of the CMOS logic gate, the first p-channel transistor configured to be body biased;

a first n-channel transistor coupled between the output terminal and reference ground;

a series p-channel transistor coupled between the output terminal and the first p-channel transistor, wherein the series p-channel transistor is configured to be body biased; and

a shunt n-channel transistor coupled between the output terminal and reference ground, wherein a gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low-power operating mode of the CMOS logic gate.

9. The CMOS logic gate of claim 8 , wherein the first p-channel transistor and the series p-channel transistor are coupled in series between the voltage source terminal and the output terminal, and wherein the first n-channel transistor and the shunt n-channel transistor are coupled in parallel between the output terminal and the reference ground.

10. The CMOS logic gate of claim 8 , wherein a body bias voltage is applied to the first p-channel transistor and the series p-channel transistor to body bias the first p-channel transistor and the series p-channel transistor.

11. The CMOS logic gate of claim 8 , further comprising a second p-channel transistor and a second n-channel transistor, wherein the second p-channel transistor is configured to be body biased, wherein the first p-channel transistor, the second p-channel transistor, and the series p-channel transistor are arranged in series between the voltage source terminal and the output terminal, and wherein the first n-channel transistor, the second n-channel transistor, and the shunt n-channel transistor are coupled in parallel between the output terminal and the reference ground.

12. The CMOS logic gate of claim 8 , further comprising a second p-channel transistor and a second n-channel transistor, wherein the second p-channel transistor is configured to be body biased, wherein the first p-channel transistor and the second p-channel transistor are arranged in parallel between the voltage source terminal and the series p-channel transistor, and wherein the first n-channel transistor, the second n-channel transistor, and the shunt n-channel transistor are coupled in parallel between the output terminal and the reference ground.

13. The CMOS logic gate of claim 8 , wherein the CMOS logic gate is a logic NAND gate, a logic NOR gate, a logic NOT gate, or a combination thereof.

14. A device, comprising an integrated circuit, the integrated circuit having:

a complementary metal-oxide-semiconductor (CMOS) logic gate including a first p-channel transistor and a first n-channel transistor, wherein the first p-channel transistor is configurable to be body biased;

a series p-channel transistor coupled between an output terminal of the CMOS logic gate and the first p-channel transistor, wherein the series p-channel transistor is configurable to be body biased; and

a shunt n-channel transistor coupled between the output terminal of the CMOS logic gate and reference ground, wherein a gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low power operating mode of the CMOS logic gate.

15. The device of claim 14 , wherein the first p-channel transistor and the series p-channel transistor are coupled in series between a voltage source terminal of the CMOS logic gate and the output terminal of the CMOS logic gate, and wherein the first n-channel transistor and the shunt n-channel transistor are coupled in parallel between the output terminal of the CMOS logic gate and the reference ground.

16. The device of claim 14 , wherein a body bias voltage is applied to the first p-channel transistor and the series p-channel transistor to body bias the first p-channel transistor and the series p-channel transistor.

17. The device of claim 14 , wherein the CMOS logic gate includes a second p-channel transistor and a second n-channel transistor, wherein the second p-channel transistor is configurable to be body biased, wherein the first p-channel transistor, the second p-channel transistor, and the series p-channel transistor are arranged in series between a voltage source terminal of the CMOS logic gate and the output terminal of the CMOS logic gate, and wherein the first n-channel transistor, the second n-channel transistor, and the shunt n-channel transistor are coupled in parallel between the output terminal of the CMOS logic gate and the reference ground.

18. The device of claim 14 , wherein the CMOS logic gate includes a second p-channel transistor and a second n-channel transistor, wherein the second p-channel transistor is configurable to be body biased, wherein the first p-channel transistor and the second p-channel transistor are arranged in parallel between a voltage source terminal of the CMOS logic gate and the series p-channel transistor, and wherein the first n-channel transistor, the second n-channel transistor, and the shunt n-channel transistor are coupled in parallel between the output terminal of the CMOS logic gate and the reference ground.

19. The device of claim 14 , wherein the CMOS logic gate is a logic NAND gate, a logic NOR gate, a logic NOT gate, or a combination thereof.

20. The device of claim 14 , wherein the integrated circuit further comprises a multiplexer having a first input terminal, a second input terminal, a select terminal, and an output terminal, wherein the first input terminal is coupled to the output terminal of the CMOS logic gate, wherein the second input terminal is couplable to a controller, wherein the select terminal is coupled to the sleep signal, and wherein the multiplexer is configured to:

set an output signal at the output terminal of the multiplexer to a signal at the first input terminal in response to the sleep signal being de-asserted; and

set an output signal at the output terminal of the multiplexer to a signal at the second input terminal in response to the sleep signal being asserted, wherein the signal at the second input terminal is a desired output value.