Estimating time of departure for round trip time with rate adaptation
A device includes a transmitter to generate a sampled stream of data for a packet at a first sample rate. A data re-sampling circuit includes a re-timer engine to determine, using a fractional rate between the first sample rate and a crystal oscillator (XO)-divided sample rate, re-timer values including a difference between pulses of a pseudo-clock corresponding to the XO-integer-divided sample rate and closest corresponding pulses of a clock corresponding to the first sample rate, and a time-shifting circuit to re-sample data values of the sampled stream of data associated with locations of the plurality of re-timer values. A comparator circuit uses the re-sampled data values to match the re-sampled data values to a corresponding data value detected in the data pattern in the frame delimiter. A timing logic uses the plurality of re-timer values and the location of the marker in the data pattern in a timing calculation.
1 . A wireless device comprising:
a transmitter to generate a sampled stream of data for a packet at a first sample rate, and to generate a marker at a location in a data pattern in a frame delimiter of the packet;
a data re-sampling circuit coupled to the transmitter, the data re-sampling circuit comprising:
a re-timer engine to determine, using a fractional conversion ratio between the first sample rate and a crystal oscillator (XO)-integer-divided sample rate, a plurality of re-timer values comprising differences between pulses of a pseudo-clock corresponding to the XO-integer-divided sample rate and closest corresponding pulses of a clock corresponding to the first sample rate; and
a time-shifting circuit to re-sample data values of the sampled stream of data associated with locations of the plurality of re-timer values:
a comparator circuit coupled to the data re-sampling circuit, the comparator circuit to use the re-sampled data values to match the re-sampled data values to a corresponding data value detected in the data pattern in the frame delimiter of the packet; and
a timing logic coupled to the comparator circuit to use the plurality of re-timer values and the location of the marker in the data pattern in a timing calculation.
2 . The wireless device of claim 1 , wherein the XO-integer-divided sample rate averages a fraction of a frequency of an integer-divided XO sample rate and the first sample rate is a non-integer sample rate.
3 . The wireless device of claim 1 , wherein the time-shifting circuit comprises a plurality of digital fractional delay filters that re-sample, using the pseudo-clock, the data values based on corresponding ones of the plurality of re-timer values.
4 . The wireless device of claim 1 , wherein the data re-sampling circuit further comprises a pseudo-clock generator to generate the pseudo-clock, the pseudo-clock generator to:
receive a phase-locked loop (PLL) clock that is derived based on the clock;
insert a pulse from the PLL clock in response to each insertion command from the re-timer engine; and
generate the pseudo-clock comprising the PLL clock with the inserted pulses, the pseudo-clock corresponding to, on average, the XO-integer-divided sample rate.
5 . The wireless device of claim 4 , wherein the re-timer engine is further to:
send an insertion command to the pseudo-clock generator.
6 . The wireless device of claim 4 , wherein the re-timer engine comprises:
a register to store a re-timer value of the plurality of re-timer values; and
a summing circuit to add the fractional conversion ratio to the re-timer value to determine a fractional re-timer value.
7 . The wireless device of claim 1 , wherein, to use the plurality of re-timer values and the location of the marker in the data pattern in the timing calculation, the timing logic is to:
modify the location of the marker in the data pattern using the plurality of re-timer values.
8 . The wireless device of claim 1 , wherein the marker corresponds to a time of departure annotation, wherein the time of departure annotation is to be used in determining a round trip time value in frame synchronization detection.
9 . A method of operating a wireless device that comprises a transmitter, a data re-sampling circuit coupled to the transmitter, a comparator circuit coupled to the data re-sampling circuit, and a timing logic coupled to the comparator circuit, wherein the method of operating the wireless device comprises:
generating, by the transmitter, a sampled stream of data for a packet at a first sample rate;
generating, by the transmitter, a marker at a location in a data pattern in a frame delimiter of the packet:
determining, by the data re-sampling circuit using a fractional conversion ratio between the first sample rate and a crystal oscillator (XO)-integer-divided sample rate, a plurality of re-timer values comprising a difference between pulses of a pseudo-clock corresponding to the XO-integer-divided sample rate and closest corresponding pulses of a clock corresponding to the first sample rate;
re-sampling, by the data re-sampling circuit, data values of the sampled stream of data associated with locations of the plurality of re-timer values;
matching, by the comparator circuit using the re-sampled data values, the re-sampled data values to a corresponding data value detected in the data pattern in the frame delimiter of the packet; and
using, by the timing logic, to the plurality of re-timer values and the location of the marker in the data pattern in a timing calculation.
10 . The method of claim 9 , wherein the XO-integer-divided sample rate averages a fraction of a frequency of an integer-divided XO sample rate and the first sample rate is a non-integer sample rate.
11 . The method of claim 9 , wherein the method of operating the wireless device further comprises re-sampling, using a plurality of fractional delay filters and the pseudo-clock, the data values based on corresponding ones of the plurality of re-timer values.
12 . The method of claim 9 , wherein the method of operating the wireless device further comprises:
receiving, by the data re-sampling circuit, a phase-locked loop (PLL) clock that is derived based on the clock;
inserting a pulse from the PLL clock in response to each insertion command received from a re-timer engine; and
generating, by the data re-sampling circuit, the pseudo-clock comprising the PLL clock with the inserted pulses, wherein the pseudo-clock corresponds to, on average, the XO-integer-divided sample rate.
13 . The method of claim 12 , wherein the method of operating the wireless device further comprises:
sending, by the re-timer engine, an insertion command to a pseudo-clock generator comprised by the re-sampling circuit.
14 . The method of claim 12 , wherein the method of operating the wireless device further comprises:
storing a re-timer value of the plural of re-timer values in a register; and
adding, by a summing circuit, to determine a fractional re-timer value, the fractional conversion ratio to the re-timer value.
15 . The method of claim 9 , wherein the method of operating the wireless device further comprises:
modifying, by the timing logic, the location of the marker in the data pattern using the plurality of re-timer values.
16 . The method of claim 9 , wherein the marker corresponds to a time of departure annotation, wherein the time of departure annotation is to be used in determining a round trip time value in frame synchronization detection.
17 . A system comprising:
an antenna; and
a wireless device adapted to gain access to a secured enclosure by transmitting data comprising a frame delimiter using the antenna, the wireless device comprising:
a transmitter to generate a sampled stream of data for a packet at a first sample rate, and to generate a marker at a location in a data pattern in a frame delimiter of the packet;
a data re-sampling circuit coupled to the transmitter, the data re-sampling circuit comprising:
a re-timer engine to determine, using a fractional rate between the first sample rate and a crystal oscillator (XO)-integer-divided sample rate, a plurality of re-timer values comprising a difference between pulses of a pseudo-clock corresponding to the XO-integer-divided sample rate and closest corresponding pulses of a clock corresponding to the first sample rate; and
a time-shifting circuit to re-sample data values of the sampled stream of data associated with locations of the plurality of re-timer values;
a comparator circuit coupled to the data re-sampling circuit, the comparator circuit to use the re-sampled data values to match the re-sampled data values to a corresponding data value detected in the data pattern in the frame delimiter of the packet; and
a timing logic coupled to a receiver to use the plurality of re-timer values and the location of the marker in the data pattern in a timing calculation.
18 . The system of claim 17 , wherein the XO-integer-divided sample rate averages a fraction of a frequency of an integer-divided XO sample rate and the first sample rate is a non-integer sample rate.
19 . The system of claim 17 , wherein the time-shifting circuit comprises a plurality of digital fractional delay filters that re-sample, using the pseudo-clock, the data values based on corresponding ones of the plurality of re-timer values.
20 . The system of claim 17 , wherein, to use the plurality of re-timer values and the location of the marker in the data pattern in the timing calculation, the timing logic is to:
modify the location of the marker in the data pattern using the plurality of re-timer values.