Regulator circuit and operating method for the same

1 . A regulator circuit comprising:

a first regulator configured to supply a first current to a VDD pad connected to a power line based on a first output voltage; and

a second regulator configured to supply a second current to the VDD pad based on a second output voltage,

wherein the first regulator operates with a first reference voltage and the second regulator operates with a second reference voltage that is lower than the first reference voltage such that the second output voltage is lower than the first output voltage by a predetermined delta voltage, and

wherein the second regulator is configured to supply the second current in response to a voltage of the VDD pad dropping below the second output voltage.

2 . The regulator circuit of claim 1 , wherein the first regulator comprises:

a first output terminal connected to the VDD pad;

a first error amplifier configured to output a first voltage by amplifying a difference between the first reference voltage and a first feedback voltage;

a first pass transistor configured to regulate an amount of the first current output through the first output terminal based on the first voltage; and

a first voltage divider having a first resistor and a second resistor connected between the first output terminal and a ground terminal and configured to feedback the first feedback voltage generated by the first resistor and the second resistor to the first error amplifier.

3 . The regulator circuit of claim 2 , wherein the second regulator comprises:

a second output terminal connected to the VDD pad;

a second error amplifier configured to output a second voltage by amplifying a difference between the second reference voltage and a second feedback voltage;

a second pass transistor configured to regulate an amount of the second current output through the second output terminal based on the second voltage; and

a second voltage divider having a third resistor and a fourth resistor connected between the second output terminal and a ground terminal and configured to feedback the second feedback voltage generated by the third resistor and the fourth resistor to the second error amplifier.

4 . The regulator circuit of claim 3 , wherein the first output terminal and the second output terminal are connected to each other.

5 . The regulator circuit of claim 4 , wherein the first output voltage is ((1+a value of the first resistor/a value of the second resistor)×the first reference voltage), and the second output voltage is ((1+a value of the third resistor/a value of the fourth resistor)×the second reference voltage), and

wherein the first resistor, the second resistor, the third resistor, the fourth resistor, the first reference voltage, and the second reference voltage are determined such that the second output voltage is smaller than the first output voltage by the delta voltage.

6 . A method of operating a regulator circuit including a first regulator and a second regulator that supply currents to a VDD pad connected to a power line, the method comprising:

supplying, by the first regulator, a current to the VDD pad in response to a voltage of the VDD pad being greater than or equal to a second output voltage; and

supplying, by both the first and second regulators, currents to the VDD pad in response to the voltage of the VDD pad dropping below the second output voltage,

wherein an output voltage of the first regulator is set to a first output voltage and an output voltage of the second regulator is set to a second output voltage that is lower than the first output voltage by a predetermined delta voltage, the first regulator using a first reference voltage and the second regulator using a second reference voltage different from the first reference voltage to establish the predetermined delta voltage.

7 . The method of claim 6 , wherein the first regulator and the second regulator supply the currents generated by the first output voltage and the second output voltage through identical paths connected to the VDD pad.

8 . The method of claim 7 , wherein the first regulator comprises a first resistor connected in series to a second resistor, and the second regulator comprises a third resistor connected in series to a fourth resistor,

wherein the first output voltage is ((1+a value of the first resistor/a value of the second resistor)×the first reference voltage), and the second output voltage is ((1+a value of the third resistor/a value of the fourth resistor)×the second reference voltage), and

wherein the first resistor, the second resistor, the third resistor, the fourth resistor, the first reference voltage, and the second reference voltage are determined such that the second output voltage is smaller than the first output voltage by the delta voltage.

9 . A regulator circuit comprising:

a first regulator configured to supply a first output voltage to a first output terminal;

a second regulator configured to supply a second output voltage, which is set to be lower than the first output voltage by a predetermined delta voltage, to a second output terminal connected to the first output terminal; and

a VDD pad connected to the first output terminal and the second output terminal,

wherein the first regulator uses a first reference voltage and the second regulator uses a second reference voltage that is lower than the first reference voltage such that the second output voltage is lower than the first output voltage by the predetermined delta voltage, and

wherein both the first regulator and the second regulator are configured to supply output voltages in response to a voltage of the VDD pad dropping below the second output voltage.

10 . The regulator circuit of claim 9 , wherein the first regulator comprises:

the first output terminal connected to the VDD pad;

a first error amplifier configured to output a first voltage by amplifying a difference between the first reference voltage and a first feedback voltage;

a first pass transistor configured to regulate an amount of a first current output through the first output terminal based on the first voltage; and

a first voltage divider having a first resistor and a second resistor connected between the first output terminal and a ground terminal and configured to feedback the first feedback voltage generated by the first resistor and the second resistor to the first error amplifier.

11 . The regulator circuit of claim 10 , wherein the second regulator comprises:

the second output terminal connected to the VDD pad;

a second error amplifier configured to output a second voltage by amplifying a difference between the second reference voltage and a second feedback voltage;

a second pass transistor configured to regulate an amount of a second current output through the second output terminal based on the second voltage; and

a second voltage divider having a third resistor and a fourth resistor connected between the second output terminal and a ground terminal and configured to feedback the second feedback voltage generated by the third resistor and the fourth resistor to the second error amplifier.

12 . The regulator circuit of claim 11 , wherein the first output voltage is ((1+a value of the first resistor/a value of the second resistor)×the first reference voltage), and the second output voltage is ((1+a value of the third resistor/a value of the fourth resistor)×the second reference voltage), and

wherein the first resistor, the second resistor, the third resistor, the fourth resistor, the first reference voltage, and the second reference voltage are determined such that the second output voltage is smaller than the first output voltage by the delta voltage.