Circuits and methods to startup and shutdown multi-level converters
A circuit suitable for use with a multi-level power converter cell that (1) charges boot capacitors at startup to a sufficient level to power level shifters and drivers that control the power switches within the cell, (2) pre-charges each fly capacitor to a target voltage, (3) provides a shut-down and/or a standby mode of operation that enables a quick re-start of operation, and (4) balances fly capacitor voltages when the fly capacitor(s) is/are not actively charge-balanced. One embodiment includes a first switchable current source coupled between a fly capacitor and an input voltage; a second switchable current source coupled between the fly capacitor and a reference potential; and a third switchable current source coupled in parallel with the fly capacitor; wherein the switchable current sources are configured to charge the fly capacitor in a first mode of operation, and to discharge the fly capacitor in a second mode of operation.
1. A circuit including:
(a) an M-level power converter cell having a set of n power switches coupled in series and configured to be coupled between an input voltage and a reference potential, where M≥3 and n≥4;
(b) an output capacitor coupled to a node between an adjacent pair of the set of n power switches and to the reference potential;
(c) one or more fly capacitors coupled to the set of n power switches, each having a top plate and a bottom plate; and
(d) for each of the one or more fly capacitors:
(1) a first switchable current source coupled to the top plate of the fly capacitor and configured to be coupled to the input voltage;
(2) a second switchable current source coupled to the bottom plate of the fly capacitor and configured to be coupled to the reference potential; and
(3) a third switchable current source coupled between the top plate and the bottom plate of the fly capacitor;
wherein the first, second, and third switchable current source are configured to charge the fly capacitor in a first mode of operation, and to discharge the fly capacitor in a second mode of operation.
2. The invention of claim 1 , wherein the power switches comprise N-type field effect transistors.
3. The invention of claim 1 , further including an inductor coupled between the output capacitor and the node.
4. The invention of claim 1 , further including a resistor coupled in parallel with at least one of the one or more fly capacitors.
5. The invention of claim 1 , wherein at least one switchable current source includes a current source and a switch coupled in series.
6. The invention of claim 1 , wherein at least one switchable current source includes a resistor and a switch coupled in series.
7. A circuit including:
(a) an M-level power converter cell having a set of n power switches coupled in series and configured to be coupled between an input voltage and a reference potential, each power switch having a control gate, where M≥3 and n≥4;
(b) an output capacitor coupled to a node between an adjacent pair of the set of n power switches and to the reference potential;
(c) one or more fly capacitors coupled to the set of n power switches, each having a top plate and a bottom plate;
(d) a set of n driver circuits each coupled to the control gate of an associated one of the set of n power switches;
(e) a set of n boot capacitors each coupled to an associated one of the set of n driver circuits and having a top plate and a bottom plate;
(f) a set of n−1 startup charger circuits, each coupled in parallel with an associated one of the set of n boot capacitors, and to a supply voltage, and configured to provide charge to the associated one of the set of n boot capacitors in a first phase of startup operation;
(g) a diode ladder coupled to a supply voltage and including a set of n−1 diodes, each diode coupled between the top plate of an associated one of the set of n boot capacitors and the top plate of an adjacent one of the set of n boot capacitors, and configured to provide charge to the associated one of the set of n boot capacitors in a second phase of startup operation and during normal operation of the M-level power converter cell;
(h) a set of n−1 switches, each coupled in parallel with an associated one of the set of n−1 diodes and configured to selectively bypass the associated one of the set of n−1 diodes.
8. The invention of claim 7 , wherein the diodes are Schottky diodes.
9. The invention of claim 7 , wherein at least one of the set of n driver circuits includes a level shifter.
10. The invention of claim 7 , wherein the set of n−1 switches comprise P-type field effect transistors.
11. The invention of claim 7 , wherein the power switches comprise N-type field effect transistors.
12. The invention of claim 7 , further including an inductor coupled between the output capacitor and the node.
13. The invention of claim 7 , further including a resistor coupled in parallel with at least one of the one or more fly capacitors.
14. The invention of claim 7 , further including, for each of the one or more fly capacitors:
(a) a first switchable current source coupled to the top plate of the fly capacitor and configured to be coupled to the input voltage;
(b) a second switchable current source coupled to the bottom plate of the fly capacitor and configured to be coupled to the reference potential; and
(c) a third switchable current source coupled between the top plate and the bottom plate of the fly capacitor;
wherein the first, second, and third switchable current source are configured to charge the fly capacitor in a first mode of operation, and to discharge the fly capacitor in a second mode of operation.
15. The invention of claim 14 , wherein at least one switchable current source includes a current source and a switch coupled in series.
16. The invention of claim 14 , wherein at least one switchable current source includes a resistor and a switch coupled in series.
17. A method of charging and discharging a fly capacitor of an M-level power converter cell having a set of n power switches coupled in series and configured to be coupled between an input voltage and a reference potential, where M≥3 and n≥4, the method including:
(a) coupling a first switchable current source between a top plate of the fly capacitor and the input voltage;
(b) coupling a second switchable current source between a bottom plate of the fly capacitor and the reference potential;
(c) coupling a third switchable current source between the top plate and the bottom plate of the fly capacitor;
(d) charging the fly capacitor in a first mode of operation by setting the first and second switchable current sources to closed conductive states, and setting the third switchable current source to an open non-conductive state; and
(e) discharging the fly capacitor in a second mode of operation by setting the first and second switchable current sources to open non-conductive states, and setting the third switchable current source to a closed conductive state.