SILICON CARBIDE TRENCH POWER DEVICE
A power semiconductor device includes a substrate having a body region and a drift layer; a trench formed in the substrate; a gate dielectric structure including a first gate insulation layer having a first dielectric constant and a second gate insulation layer having a second dielectric constant different from the first dielectric constant; and a conductive material provided within the trench over the gate dielectric structure.
1 . A method for fabricating a power semiconductor device, the method comprising:
etching a trench in a substrate having a body region and a drift layer;
depositing a first dielectric material over the substrate and into the trench, the first dielectric material having a first dielectric constant;
etching the first dielectric material to expose a sidewall of the trench and provide the first dielectric material with a first thickness;
forming a second dielectric material over the sidewall of the trench, the second dielectric material having a second dielectric constant different from the first dielectric constant; and
providing a conductive material within the trench and over the first dielectric material and the second dielectric material to from a gate,
the first dielectric material and the second dielectric material defining a gate dielectric structure for the gate.
2 . The method of claim 1 , wherein the substrate is a silicon carbide substrate, the method further comprising:
etching the first dielectric material to reduce the first dielectric material to a second thickness.
3 . The method of claim 2 , wherein the first dielectric material is provided with a lower portion and a side portion that wrap a bottom corner of the conductive material.
4 . The method of claim 2 , wherein the first dielectric material has a dielectric constant of at least 4, and the second dielectric material is silicon oxide.
5 . The method of claim 4 , wherein the first gate-dielectric material includes silicon nitride.
6 . The method of claim 4 , wherein the first gate-dielectric material includes aluminum nitride.
7 . The method of claim 2 , further comprising:
forming a compensation region below the trench in the drift layer, the compensation region having a conductivity that is opposite to that of the drift layer.
8 . A method for fabricating a power semiconductor device, the method comprising:
etching a trench in a substrate having a body region and a drift layer;
forming a gate dielectric structure including a first gate insulation layer having a first dielectric constant and a second gate insulation layer having a second dielectric constant that is different from the first dielectric constant; and
providing a conductive material within the trench and over the gate dielectric structure to make a gate.
9 . The method of claim 8 , wherein the substrate is a silicon carbide substrate, the first gate insulation layer includes silicon oxide, and the second gate insulation layer includes silicon nitride or aluminum nitride.
10 . The method of claim 8 , wherein the second gate insulation layer wraps around a bottom corner of the conductive material to reduce electric field buildup at the bottom corner during an operation.
11 . A method comprising:
forming a body region and a drift layer in a substrate;
forming a trench in the substrate;
forming a gate dielectric structure including a first gate insulation layer having a first dielectric constant and a second gate insulation layer having a second dielectric constant different from the first dielectric constant; and
forming a conductive material provided within the trench over the gate dielectric structure.
12 . The method of claim 11 , wherein the substrate is a silicon carbide substrate, and the first gate insulation layer is disposed over a sidewall of the trench and the second gate insulation layer is disposed over a bottom of the trench.
13 . The method of claim 12 , wherein the first gate insulation layer includes silicon oxide, and the second gate insulation layer includes a dielectric material having a dielectric constant higher than that of the silicon oxide.
14 . The method of claim 13 , wherein the second gate insulation layer includes silicon nitride.
15 . The method of claim 13 , wherein the second gate insulation layer includes aluminum nitride.
16 . The method of claim 11 , wherein the substrate is a silicon carbide substrate, and the first gate insulation layer extends below the body region and into the drift layer.
17 . The method of claim 11 , wherein the first gate insulation layer includes silicon oxide, and the second gate insulation layer includes a dielectric material having a dielectric constant greater than that of the silicon oxide, the second gate insulation layer being configured to reduce electric field buildup in the trench during operation.
18 . The method of claim 17 , wherein the second gate insulation layer includes a lower portion and a side portion that wrap a bottom corner of the conductive material provided in the trench, the side portion being configured to reduce electric field buildup at the bottom corner during power device operation.
19 . The method of claim 18 , wherein the side portion of the second gate insulation layer has a height of at least 0.05 um.
20 . The method of claim 17 , further comprising:
forming a compensation region provided below the trench in the drift layer, the compensation region having a conductivity opposite to that of the drift layer.