Non-complementary active clamp flyback (ACF) primary field-effect transistors (FET) control
In an example embodiment, a method comprising identifying, by a primary-side controlled Universal Serial Bus Power Delivery (USB-PD) alternating current to direct current (AC-DC) converter, a first pulse, wherein the first pulse is received from a pulse transformer. The method further includes determining that a threshold duration of time is satisfied. In response to determining that the threshold duration of time is satisfied, the method includes identifying a second pulse, wherein the second pulse is received from the pulse transformer. The first pulse and the second pulse are used for control of a high-side field effect transistor (FET) and a low-side FET, where the high-side FET is coupled to an active clamp flyback (ACF) circuit and the low-side FET is coupled to a flyback transformer of the USB-PD AC-DC converter. In response to identifying the second pulse, the method further includes controlling operation of the high-side FET or the low-side FET.
1 . A method comprising:
identifying, by a primary-side controlled Universal Serial Bus Power Delivery (USB-PD) alternating current to direct current (AC-DC) converter, a first pulse, wherein the first pulse is received from a pulse transformer;
determining that a threshold duration of time is satisfied;
in response to determining that the threshold duration of time is satisfied, identifying a second pulse, wherein the second pulse is received from the pulse transformer;
wherein the first pulse and the second pulse are used for control of a high-side field effect transistor (FET) and a low-side FET, wherein the high-side FET is coupled to an active clamp flyback (ACF) circuit of the USB-PD AC-DC converter, and wherein the low-side FET is coupled to a flyback transformer of the USB-PD AC-DC converter; and
in response to identifying the second pulse, controlling operation of the high-side FET or the low-side FET.
2 . The method of claim 1 , wherein the USB-PD AC-DC converter is initially controlling the operation of the low-side FET.
3 . The method of claim 1 , wherein controlling the operation of the high-side FET or the low-side FET further comprises:
controlling the operation of the high-side FET.
4 . The method of claim 1 , further comprising:
identifying a third pulse, wherein the third pulse is received from the pulse transformer, and wherein the third pulse is a positive pulse; and
in response to identifying the third pulse, controlling the operation of the high-side FET or the low-side FET.
5 . The method of claim 4 , wherein controlling the operation of the high-side FET or the low-side FET further comprises:
controlling the operation of the low-side FET.
6 . The method of claim 1 , wherein the first pulse is a negative pulse, and wherein the second pulse is a negative pulse.
7 . The method of claim 1 , further comprising:
determining that the threshold duration of time is not satisfied;
identifying a third pulse, wherein the third pulse is received from the pulse transformer, and wherein the third pulse is a positive pulse; and
controlling the operation of the low-side FET.
8 . A Universal Serial Bus Power Delivery (USB-PD) alternating current to direct current (AC-DC) power supply comprising:
a flyback transformer;
an active clamp flyback (ACF) circuit;
a high-side field effect transistor (FET) coupled between the flyback transformer and the ACF circuit;
a low-side FET coupled to the flyback transformer;
a pulse transformer; and
a primary-side controller coupled to receive signals from the pulse transformer and to control operation of the high-side FET and the low-side FET, wherein the primary-side controller is to:
identify a first pulse, wherein the first pulse is received from the pulse transformer;
determine that a threshold duration of time is satisfied;
in response to determining that the threshold duration of time is satisfied, identify a second pulse, wherein the second pulse is received from the pulse transformer; and
in response to identifying the second pulse, control operation of the high-side FET or the low-side FET.
9 . The USB-PD AC-DC power supply of claim 8 , wherein the USB-PD power supply is initially controlling the operation of the low-side FET.
10 . The USB-PD AC-DC power supply of claim 8 , wherein, to control the operation of the high-side FET or the low-side FET, the primary-side controller is further to:
control the operation of the high-side FET.
11 . The USB-PD AC-DC power supply of claim 8 , wherein the primary-side controller is further to:
identify a third pulse, wherein the third pulse is received from the pulse transformer, and wherein the third pulse is a positive pulse; and
in response to identifying the third pulse, control the operation of the high-side FET or the low-side FET.
12 . The USB-PD AC-DC power supply of claim 11 , wherein, to control the operation of the high-side FET or the low-side FET, the primary-side controller is further to:
control the operation of the low-side FET.
13 . The USB-PD AC-DC power supply of claim 8 , wherein the first pulse is a negative pulse, and wherein the second pulse is a negative pulse.
14 . The USB-PD AC-DC power supply of claim 8 , wherein the primary-side controller is further to:
determine that the threshold duration of time is not satisfied;
identify a third pulse, wherein the third pulse is received from the pulse transformer, and wherein the third pulse is a positive pulse; and
control the operation of the low-side FET.
15 . A Universal Serial Bus Power Delivery (USB-PD) flyback converter system, the system comprising:
a flyback transformer;
an active clamp flyback (ACF) circuit;
a high-side field-effect transistor (FET) coupled between the flyback transformer and the ACF circuit;
a low-side FET coupled to the flyback transformer;
a pulse transformer; and
a primary-side controller coupled to receive signals from the pulse transformer and to control operation of the high-side FET and the low-side FET, the primary-side controller configured to:
identify a first pulse, wherein the first pulse is received from the pulse transformer;
determine that a threshold duration of time is satisfied;
in response to determining that the threshold duration of time is satisfied, identify a second pulse, wherein the second pulse is received from the pulse transformer; and
in response to identifying the second pulse, control operation of the high-side FET or the low-side FET.
16 . The system of claim 15 , wherein the system is initially controlling the operation of the low-side FET.
17 . The system of claim 15 , wherein to control the operation of the high-side FET or the low-side FET, the primary-side controller is to control the operation of the high-side FET.
18 . The system of claim 15 , wherein the primary-side controller is further configured to:
identify a third pulse, wherein the third pulse is received from the pulse transformer, and wherein the third pulse is a positive pulse; and
in response to identifying the third pulse, control the operation of the high-side FET or the low-side FET.
19 . The system of claim 18 , wherein to control the operation of the high-side FET or the low-side FET, the primary-side controller is to control the operation of the low-side FET.
20 . The system of claim 15 , wherein the primary-side controller is further configured to:
determine that the threshold duration of time is not satisfied;
identify a third pulse, wherein the third pulse is received from the pulse transformer, and wherein the third pulse is a positive pulse; and
control the operation of the low-side FET.