IP Library Granted Patent US 12,505,049
Granted Patent B2
US 12,505,049 · App. 18/334,981 · Granted Dec 23, 2025

Hierarchical memory system

Inventors: Heekwon Park (San Jose, CA); Changho Choi (San Jose, CA); Yang Seok Ki (Palo Alto, CA)
Assignee: Samsung Electronics Co., Ltd.
G06F12/123
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Quick Facts
Patent No.
US 12,505,049
App. No.
18/334,981
Granted
Dec 23, 2025
Kind
B2
Abstract

A hierarchical memory system and method. In some embodiments, the method includes: demoting a first page of data from a fast memory to a slow memory; promoting the first page of data from the slow memory to an intermediate memory zone; and promoting the first page of data from the intermediate memory zone to the fast memory, wherein the intermediate memory zone includes a virtual zone within the slow memory.

Claims (86)

1 . A method, comprising:

demoting a first page of data from a first memory to a second memory;

promoting the first page of data from the second memory to an intermediate memory zone; and

promoting the first page of data from the intermediate memory zone to the first memory,

wherein:

the intermediate memory zone comprises a virtual zone within the second memory, and

the promoting of the first page of data to the first memory comprises promoting the first page of data to the first memory based on an access count of the first page of data.

2 . The method of claim 1 , wherein:

the first memory is faster than the second memory;

the demoting of the first page of data from the first memory to the second memory comprises a first demotion of the first page of data; and

the method further comprises:

performing a second demotion of the first page of data, the second demotion of the first page of data comprising demoting the first page of data from the first memory to the second memory; and

increasing a size of the intermediate memory zone, based on the first demotion and the second demotion.

3 . The method of claim 1 , further comprising:

determining that a page utilization metric in the intermediate memory zone is less than a threshold; and

decreasing a size of the intermediate memory zone.

4 . The method of claim 1 , further comprising:

determining that a page utilization metric in the intermediate memory zone is less than a threshold; and

decreasing a size of the intermediate memory zone,

wherein the decreasing of the size of the intermediate memory zone comprises promoting a second page of data from the intermediate memory zone to the first memory.

5 . The method of claim 1 , wherein the second memory is managed by a system memory manager.

6 . The method of claim 1 , wherein:

the second memory comprises persistent memory; and

the second memory is managed by a file system.

7 . The method of claim 1 , further comprising:

determining a first access count, for a second page of data, in the intermediate memory zone; and

determining a second access count, for the second page of data, in the intermediate memory zone.

8 . The method of claim 7 , further comprising:

determining a third access count, for a third page of data, in the intermediate memory zone;

determining that the third access count is greater than the second access count; and

based on determining that the third access count is greater than the second access count, promoting the third page of data from the intermediate memory zone to the first memory.

9 . The method of claim 7 , further comprising:

determining a third access count, for a third page of data, in the intermediate memory zone;

determining a fourth access count, for the third page of data, in the intermediate memory zone;

determining that a sum of the third access count and the fourth access count is greater than a sum of the first access count and the second access count; and

based on determining that a sum of the third access count and the fourth access count is greater than a sum of the first access count and the second access count, promoting the third page of data from the intermediate memory zone to the first memory.

10 . The method of claim 7 , further comprising:

determining a third access count, for a third page of data, in the intermediate memory zone;

determining a fourth access count, for the third page of data, in the intermediate memory zone;

determining that a number of nonzero values among the third access count and the fourth access count is greater than a number of nonzero values among the first access count and the second access count; and

based on determining that a number of nonzero values among the third access count and the fourth access count is greater than a number of nonzero values among the first access count and the second access count, promoting the third page of data from the intermediate memory zone to the first memory.

11 . The method of claim 7 , wherein:

the second memory comprises persistent memory;

the second memory is managed by a file system; and

the method further comprises storing the first access count, and the second access count in a file node corresponding to the second page of data.

12 . A system, comprising:

a processing circuit; and

memory, operatively connected to the processing circuit and storing instructions that, when executed by the processing circuit, cause the system to perform a method, the method comprising:

demoting a first page of data from a first memory to a second memory;

promoting the first page of data from the second memory to an intermediate memory zone; and

promoting the first page of data from the intermediate memory zone to the first memory,

wherein:

the intermediate memory zone is a virtual zone within the second memory, and

the promoting of the first page of data to the first memory comprises promoting the first page of data to the first memory based on an access count of the first page of data.

13 . The system of claim 12 , wherein:

the first memory is faster than the second memory;

the demoting of the first page of data from the first memory to the second memory is a first demotion of the first page of data; and

the method further comprises:

performing a second demotion of the first page of data, the second demotion of the first page of data comprising demoting the first page of data from the first memory to the second memory; and

increasing a size of the intermediate memory zone, based on the first demotion and the second demotion.

14 . The system of claim 12 , wherein the method further comprises:

determining that a page utilization metric in the intermediate memory zone is less than a threshold; and

decreasing a size of the intermediate memory zone.

15 . The system of claim 12 , wherein the method further comprises:

determining that a page utilization metric in the intermediate memory zone is less than a threshold; and

decreasing a size of the intermediate memory zone,

wherein the decreasing of the size of the intermediate memory zone comprises promoting a second page of data from the intermediate memory zone to the first memory.

16 . The system of claim 12 , wherein the second memory is managed by a system memory manager.

17 . The system of claim 12 , wherein:

the second memory comprises persistent memory; and

the second memory is managed by a file system.

18 . A device, comprising:

a processing circuit;

a first memory; and

a second memory,

the device being configured to:

demote a first page of data from the first memory to the second memory;

promoting the first page of data from the second memory to an intermediate memory zone; and

promote the first page of data from the intermediate memory zone to the first memory,

wherein:

the intermediate memory zone is a virtual zone within the second memory, and

the promoting of the first page of data to the first memory comprises promoting the first page of data to the first memory based on an access count of the first page of data.

19 . The device of claim 18 , wherein the second memory is managed by a system memory manager.

20 . The device of claim 18 , wherein:

the second memory comprises persistent memory; and

the second memory is managed by a file system.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2023
From: PARK, HEEKWON; CHOI, CHANGHO; KI, YANG SEOK
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 064428/0539 →
Continuity (2)
Provisional Application 63457350 · Apr 5, 2023
Related Publication 20240338324A1 · Oct 10, 2024
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