IP Library Patent Application 18335009
Patent Application
App. No. 18/335,009

LOW POWER CLOCK MULTIPLEXER IN MICROCONTROLLER WITH SELECTABLE POWER DOMAIN OUTPUT

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Quick Facts
Patent No.
US None
App. No.
18/335,009
Abstract

Systems and methods described herein fan out a source clock signal within the MCU to produce a plurality of clock signals. The systems and methods distribute the plurality of clock signals to a plurality of input/output (I/O) groups within the MCU, wherein each of the plurality of VO groups correspond to a different one of a plurality of power domains of the MCU. The systems and method provide the plurality of clock signals to a plurality of peripherals coupled to the plurality of I/O groups.

Claims (45)

1 . A method performed by an electronic circuit within a microcontroller unit (MCU), the method comprising:

fanning out a source clock signal within the MCU to produce a plurality of clock signals;

distributing the plurality of clock signals to a plurality of input/output (I/O) groups within the MCU, wherein each one of the plurality of I/O groups correspond to a different one of a plurality of power domains of the MCU; and

providing the plurality of clock signals to a plurality of peripherals coupled to the plurality of I/O groups.

2 . The method of claim 1 , wherein the source clock signal is a first source clock signal corresponding to a first clock domain and the plurality of clock signals are a plurality of first clock signals, the method further comprising:

fanning out a second source clock signal corresponding to a second clock domain within the MCU to produce a plurality of second clock signals, wherein the first source clock signal and the second source clock signal operate at different clock frequencies;

distributing the plurality of second clock signals to the plurality of I/O groups; and

providing the plurality of second clock signals to the plurality of peripherals coupled to the plurality of I/O groups.

3 . The method of claim 1 , wherein the source clock signal is a low power clock and each one of the plurality of clock signals operate as a low power clock to one or more of the plurality of peripherals while operating a low power state.

4 . The method of claim 1 , wherein each one of the plurality of power domains are based on one of a plurality of device specifications corresponding to the plurality of peripherals.

5 . The method of claim 1 , further comprising:

turning off power to a first peripheral of the plurality of peripherals; and

turning off one of the plurality of clock signals corresponding to the first peripheral in response to turning off the power to the first peripheral.

6 . The method of claim 1 , wherein the MCU comprises a multiplexer to fan out the source clock signal to produce the plurality of clock signals.

7 . The method of claim 1 , wherein the source clock signal is generated external to the MCU.

8 . A system comprising a microcontroller unit (MCU), configured to:

fan out a source clock signal to produce a plurality of clock signals;

distribute the plurality of clock signals to a plurality of input/output (I/O) groups within the MCU, wherein each of the plurality of I/O groups correspond to a different one of a plurality of power domains of the MCU; and

provide the plurality of clock signals to a plurality of peripherals coupled to the plurality of I/O groups and external to the MCU.

9 . The system of claim 8 , wherein the source clock signal is a first source clock signal that corresponds to a first clock domain and the plurality of clock signals are a plurality of first clock signals, the MCU further configured to:

fan out a second source clock signal that corresponds to a second clock domain within the MCU to produce a plurality of second clock signals, wherein the first source clock signal and the second source clock signal operate at different clock frequencies;

distribute the plurality of second clock signals to the plurality of I/O groups; and

provide the plurality of second clock signals to the plurality of peripherals coupled to the plurality of I/O groups.

10 . The system of claim 8 , further comprising:

one or more clock signal boosters that adjust a voltage level of one or more of the plurality of clock signals prior to being sent to one or more of the plurality of peripherals.

11 . The system of claim 8 , wherein each one of the plurality of power domains are based on one of a plurality of device specifications corresponding to the plurality of peripherals.

12 . The system of claim 8 , wherein the MCU is further configured to:

turn off power to a first peripheral of the plurality of peripherals; and

turn off one of the plurality of clock signals that correspond to the first peripheral based on the power turned off to the first peripheral.

13 . The system of claim 8 , wherein the MCU comprises a multiplexer to fan out the source clock signal to produce the plurality of clock signals.

14 . The system of claim 8 , wherein the source clock signal is generated external to the MCU.

15 . A microcontroller unit (MCU), configured to:

fan out a source clock signal to produce a plurality of clock signals;

distribute the plurality of clock signals to a plurality of input/output (I/O) groups within the MCU, wherein each of the plurality of I/O groups correspond to a different one of a plurality of power domains of the MCU; and

provide the plurality of clock signals to a plurality of peripherals coupled to the plurality of I/O groups and external to the MCU.

16 . The MCU of claim 15 , wherein the source clock signal is a first source clock signal that corresponds to a first clock domain and the plurality of clock signals are a plurality of first clock signals, the MCU further configured to:

fan out a second source clock signal that corresponds to a second clock domain within the MCU to produce a plurality of second clock signals, wherein the first source clock signal and the second source clock signal operate at different clock frequencies;

distribute the plurality of second clock signals to the plurality of I/O groups; and

provide the plurality of second clock signals to the plurality of peripherals coupled to the plurality of I/O groups.

17 . The MCU of claim 15 , wherein the source clock signal is a low power clock and each one of the plurality of clock signals operate as a low power clock to one or more of the plurality of peripherals while operating a low power state.

18 . The MCU of claim 15 , wherein each one of the plurality of power domains are based on one of a plurality of device specifications corresponding to the plurality of peripherals.

19 . The MCU of claim 15 , wherein the MCU is further configured to:

turn off power to a first peripheral of the plurality of peripherals; and

turn off one of the plurality of clock signals that correspond to the first peripheral based on the power turned off to the first peripheral.

20 . The MCU of claim 15 , wherein the MCU comprises a multiplexer to fan out the source clock signal to produce the plurality of clock signals.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Oct 21, 2025
From: CYPRESS SEMICONDUCTOR CORPORATION; INFINEON TECHNOLOGIES AMERICAS CORP.
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 073140/0554 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2025
From: LIANG, JIAWEI
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 070563/0633 →