IP Library Granted Patent US 12,438,452
Granted Patent B2
US 12,438,452 · App. 18/336,695 · Granted Oct 7, 2025

Implementing power factor correction with single-stage flyback converters operating with a variable switching frequency

Inventors: Rashed Ahmed (Cedar Park, CA); Harish Subramanya (El Segundo, CA); Ganesh Subramaniam (Cupertino, CA); Madhan Kumar Kuppaswamy (Bangalore, IN)
Assignee: Cypress Semiconductor Corporation
H02M1/4266H02M1/0009H02M1/007H02M3/003H02M3/33515H02M3/33507H02M3/33523
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Quick Facts
Patent No.
US 12,438,452
App. No.
18/336,695
Granted
Oct 7, 2025
Kind
B2
Abstract

Controlling power factor correction (PFC) in a flyback converter is described. In one embodiment, an apparatus includes a flyback converter configured to operate with a variable switching frequency. The flyback converter includes a signal transformer, a primary side including a primary-side controller coupled to the signal transformer, and a secondary side including a secondary-side controller coupled to the signal transformer. The secondary-side controller is configured at least to cause a control signal to be generated based on a set of parameters. The control signal controls power factor correction (PFC) for the flyback converter.

Claims (38)

1. An apparatus comprising:

a flyback converter configured to operate with a variable switching frequency, the flyback converter comprising:

a signal transformer;

a primary side comprising a primary-side controller coupled to the signal transformer; and

a secondary side comprising a secondary-side controller coupled to the signal transformer, wherein the secondary-side controller is configured at least to cause a control signal to be generated based on a set of parameters, and wherein the control signal controls power factor correction (PFC) for the flyback converter;

wherein the flyback converter is a single-stage flyback converter operating with the variable switching frequency in a critical conduction mode (CrCM).

2. The apparatus of claim 1 , wherein the secondary-side controller further comprises a ramp voltage generator comprising a programmable digital-to-analog converter (DAC) coupled to a DAC controller configured to generate, based on the set of parameters, an analog signal corresponding to the control signal.

3. The apparatus of claim 2 , wherein the programmable DAC is a current DAC.

4. The apparatus of claim 2 , wherein the secondary-side controller further comprises an error amplifier configured to generate an error amplifier signal, and wherein the control signal is further generated based on the error amplifier signal.

5. The apparatus of claim 4 , wherein the secondary-side controller further comprises a comparator configured to receive the analog signal and the error amplifier signal, and generate the control signal to have a duty cycle defined by the error amplifier signal.

6. The apparatus of claim 4 , wherein the secondary-side controller further comprises a resistor divider, and wherein the error amplifier is configured to generate the error amplifier signal by comparing a fixed reference value to an output reference value provided by the resistor divider.

7. The apparatus of claim 4 , wherein the secondary-side controller further comprises a compensator comprising a resistor-capacitor (RC) network and the error amplifier signal.

8. The apparatus of claim 2 , wherein the secondary-side controller is further configured to initialize the ramp voltage generator of the secondary-side controller by configuring the programmable DAC in accordance with a set of configuration settings for generating the analog signal.

9. The apparatus of claim 2 , wherein the set of parameters comprises an input voltage determined by the DAC controller based on a signal received from a sense node, an output voltage received by the DAC controller from a node of a resistor divider, and an output current received by the DAC controller from a current sense amplifier coupled to a pair of current sense nodes.

10. The apparatus of claim 1 , wherein:

the flyback converter further comprises a flyback transformer coupled between the primary side and the secondary side;

the primary side further comprises a power switch; and

the secondary side further comprises a diode.

11. The apparatus of claim 10 , wherein the primary-side controller comprises a comparator having a pair of input terminals coupled to a primary-side winding of the signal transformer, and an output terminal coupled to the power switch.

12. The apparatus of claim 1 , wherein the apparatus comprises a Universal Serial Bus Power Delivery (USB-PD) power adapter.

13. The apparatus of claim 1 , further comprising a rectifier to generate a direct current (DC) output based on an alternating current (AC) input received from an AC source.

14. A method comprising:

initializing a ramp voltage generator of a secondary-side controller of a Universal Serial Bus Power Delivery (USB-PD) flyback converter configured to operate with a variable switching frequency, wherein the USB-PD flyback converter further comprises a signal transformer coupled to the secondary-side controller, and a primary-side controller coupled to the signal transformer; and

causing a control signal to be generated based on a set of parameters, wherein the control signal controls power factor correction (PFC) for the USB-PD flyback converter.

15. The method of claim 14 , wherein causing the control signal to be generated further comprises causing the control signal to be generated based on an analog signal received from a ramp voltage generator comprising a programmable digital-to-analog converter (DAC) coupled to a DAC controller, and an error amplifier signal from an error amplifier of the secondary-side controller, wherein the analog signal is generated based on the set of parameters, and wherein the control signal has a duty cycle defined by the error amplifier signal.

16. The method of claim 15 , wherein initializing the ramp voltage generator further comprises configuring the programmable DAC in accordance with a set of configuration settings for generating the analog signal.

17. The method of claim 15 , wherein the set of parameters comprises an input voltage determined by the DAC controller based on a signal received from a sense node, an output voltage received by the DAC controller from a node of a resistor divider, and an output current received by the DAC controller from a current sense amplifier coupled to a pair of current sense nodes.

18. The method of claim 15 , wherein the USB-PD flyback converter is a single-stage flyback converter operating with the variable switching frequency in a critical conduction mode (CrCM).

19. A power adapter comprising:

a rectifier configured to generate a direct current (DC) output based on an alternating current (AC) input received from an AC source; and

a flyback converter configured to operate with a variable switching frequency, the flyback converter comprising:

a flyback transformer;

a signal transformer;

a primary side comprising:

a primary-side controller coupled to the flyback transformer and the signal transformer; and

a power switch coupled to the primary-side controller; and

a secondary side comprising a secondary-side controller coupled to the flyback transformer and the signal transformer, wherein the secondary-side controller is configured at least to cause a control signal to be generated based on a set of parameters, and wherein the control signal controls power factor correction (PFC) for the flyback converter;

wherein the flyback converter is a single-stage flyback converter operating with the variable switching frequency in a critical conduction mode (CrCM).

Assignments (2)
MERGER Recorded Nov 14, 2025
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 073571/0456 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2023
From: AHMED, RASHED; KUPPASWAMY, MADHAN KUMAR; SUBRAMANIAM, GANESH; SUBRAMANYA, HARISH
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 064410/0494 →
Continuity (2)
Provisional Application 63446994 · Feb 20, 2023
Related Publication 20240283352A1 · Aug 22, 2024
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