HETEROGENEOUS REPRESENTATION OF PARAMETRIZED QUANTUM CIRCUITS
A system, method and computer program product for serializing and deserializing quantum circuits are provided. A high-level representation of a parameterized quantum circuit includes parameter data and circuit structure data. The high-level representation is serialized into a heterogenous representation that includes separate representation sections for the circuit structure and the parameter data of the parametrized circuit. The separate representation sections can be defined using different data formats. The circuit structure data and the parameter data can be extracted separately from the heterogeneous representation. The circuit structure and the parameter data of the parameterized circuit can then be deserialized separately. The deserialized representations can be combined to provide a quantum circuit object that can be used for execution by quantum hardware and/or a quantum simulator.
1 . A method comprising:
identifying circuit structure data in a quantum circuit representation, the circuit structure data defining an arrangement of a plurality of quantum gates in a quantum circuit to be executed by a quantum simulator or quantum hardware;
identifying parameter data in the quantum circuit representation, the parameter data defining a plurality of parameters of the quantum circuit;
generating a parsed circuit structure representation by parsing the circuit structure data;
generating a parsed parameter representation by parsing the parameter data, wherein the parameter data is parsed separately from the circuit structure data; and
combining the parsed circuit structure representation and the parsed parameter representation into a combined quantum circuit.
2 . The method of claim 1 , further comprising sending a compiled quantum circuit to the quantum simulator or quantum hardware for execution, wherein the compiled quantum circuit is the combined quantum circuit or the compiled quantum circuit is generated by compiling the combined quantum circuit.
3 . The method of claim 1 , wherein the circuit structure data and the parameter data are defined using different formats.
4 . The method of claim 1 , wherein the circuit structure data is defined using a text-based format.
5 . The method of claim 1 , wherein the parameter data is defined using a binary format.
6 . The method of claim 1 , wherein combining the parsed circuit structure representation and the parsed parameter representation comprises, for each parameter in the plurality of parameters:
determining a corresponding parameter location in the parsed circuit structure data; and
inserting a parameter value of that parameter at the corresponding parameter location.
7 . The method of claim 6 , further comprising:
determining an associative map associated with the quantum circuit representation; and
determining the corresponding parameter value for each parameter location using the associative map.
8 . The method of claim 7 , further comprising:
receiving at least one request message for the execution of the quantum circuit;
identifying delimiter data in the at least one request message; and
identifying the associative map in the delimiter data.
9 . The method of claim 1 , further comprising:
receiving at least one request message for the execution of the quantum circuit; and
identifying the circuit structure data and the parameter data in the at least one request message.
10 . The method of claim 1 , wherein the quantum circuit representation is a high-level quantum circuit representation defined in a high-level programming language and the method comprises:
translating the circuit structure data into an intermediate circuit structure representation defined in a quantum intermediate representation language;
generating the parsed circuit structure representation by parsing the intermediate circuit structure representation;
translating the parameter data into an intermediate parameter representation defined in a specified data format; and
generating the parsed parameter representation by parsing the intermediate parameter representation.
11 . The method of claim 10 , further comprising:
receiving at least one request message containing the high-level quantum circuit representation; and
extracting the circuit structure data and the parameter data from the at least one request message.
12 . A computer system comprising a processor, a computer-readable memory, and a non-transitory computer readable medium storing computer-executable instructions, which, when executed by the processor, cause the processor to carry out a method comprising:
identifying circuit structure data in a quantum circuit representation, the circuit structure data defining an arrangement of a plurality of quantum gates in a quantum circuit to be executed by a quantum simulator or quantum hardware;
identifying parameter data in the quantum circuit representation, the parameter data defining a plurality of parameters of the quantum circuit;
generating a parsed circuit structure representation by parsing the circuit structure data;
generating a parsed parameter representation by parsing the parameter data, wherein the parameter data is parsed separately from the circuit structure data; and
combining the parsed circuit structure representation and the parsed parameter representation into a combined quantum circuit.
13 . The computer system of claim 12 , wherein the method further comprises sending a compiled quantum circuit to the quantum simulator or quantum hardware for execution, wherein the compiled quantum circuit is the combined quantum circuit or the compiled quantum circuit is generated by compiling the combined quantum circuit.
14 . The computer system of claim 12 , wherein the circuit structure data is defined using a text-based format and the parameter data is defined using a binary format.
15 . The computer system of claim 12 , wherein combining the parsed circuit structure representation and the parsed parameter representation comprises, for each parameter in the plurality of parameters:
determining a corresponding parameter location in the parsed circuit structure data; and
inserting a parameter value of that parameter at the corresponding parameter location.
16 . The computer system of claim 15 , wherein the method further comprises:
determining an associative map associated with the quantum circuit representation; and
determining the corresponding parameter value for each parameter location using the associative map.
17 . The computer system of claim 16 , wherein the method further comprises:
receiving at least one request message for the execution of the quantum circuit;
identifying delimiter data in the at least one request message; and
identifying the associative map in the delimiter data.
18 . The computer system of claim 12 , wherein the method further comprises:
receiving at least one request message for the execution of the quantum circuit; and
identifying the circuit structure data and the parameter data in the at least one request message.
19 . The computer system of claim 12 , wherein the quantum circuit representation is a high-level quantum circuit representation defined in a high-level programming language and the method comprises:
translating the circuit structure data into an intermediate circuit structure representation defined in a quantum intermediate representation language;
generating the parsed circuit structure representation by parsing the intermediate circuit structure representation;
translating the parameter data into an intermediate parameter representation defined in a specified data format; and
generating the parsed parameter representation by parsing the intermediate parameter representation.
20 . The computer system of claim 19 , wherein the method further comprises:
receiving at least one request message containing the high-level quantum circuit representation; and
extracting the circuit structure data and the parameter data from the at least one request message.