Dead-time calibration scheme for active clamp flyback (ACF) primary field-effect transistors (FET)
A method comprising controlling operation, by a secondary-side controlled Universal Serial Bus Power Delivery (USB-PD) alternating current to direct current (AC-DC) converter, a low-side field-effect transistor (FET). In response to controlling operation of the low-side FET, the method further includes triggering a zero-cross detection circuit. The method further includes measuring a first period of time between controlling operation of the low-side FET and triggering the zero-cross detection circuit. The method further includes measuring a second period of time between controlling operation of a high-side FET and triggering the zero-cross detection circuit. The method further includes adjusting a third period of time based on the first period of time and the second period of time, wherein the third period of time corresponds to a dead time between controlling operation of the high-side FET and the low-side FET.
1 . A method comprising:
controlling operation, in a secondary-side controlled Universal Serial Bus Power Delivery (USB-PD) alternating current to direct current (AC-DC) converter, of a low-side field-effect transistor (FET);
in response to controlling operation of the low-side FET, triggering a zero-cross detection circuit;
measuring a first period of time between controlling operation of the low-side FET and triggering the zero-cross detection circuit;
measuring a second period of time between controlling operation of a high-side FET and triggering the zero-cross detection circuit; and
adjusting a third period of time based on the first period of time and the second period of time, wherein the third period of time corresponds to a dead time between controlling operation of the high-side FET and the low-side FET.
2 . The method of claim 1 , wherein the third period of time corresponds to an optimum timing for zero voltage switching.
3 . The method of claim 1 , wherein the USB-PD AC-DC converter is initially controlling the operation of the low-side FET.
4 . The method of claim 1 , wherein the triggering of the zero-cross detection circuit comprises determining that a respective voltage of the low-side FET or the high-side FET reaches zero.
5 . The method of claim 1 , wherein controlling the operation of the low-side FET comprises turning off a control phase of the low-side FET.
6 . The method of claim 1 , wherein controlling the operation of the high-side FET comprises turning off a control phase of the high-side FET.
7 . The method of claim 1 , wherein the third period of time is received by a primary-side controller for controlling operation of the high-side FET or the low-side FET.
8 . The method of claim 1 , wherein the zero-cross detection circuit is performed by a secondary-side controller of the USB-PD AC-DC converter.
9 . A Universal Serial Bus Power Delivery (USB-PD) alternating current to direct current (AC-DC) power supply comprising:
a flyback transformer;
an active clamp flyback (ACF) circuit;
a high-side field effect transistor (FET) coupled between the flyback transformer and the ACF circuit;
a low-side FET coupled to the flyback transformer;
a pulse transformer;
a primary-side controller coupled to receive signals from the pulse transformer and to control operation of the high-side FET and the low-side FET; and
a secondary-side controller, wherein the secondary-side controller is to:
trigger a zero-cross detection circuit;
measure a first period of time between controlling operation of the low-side FET and triggering the zero-cross detection circuit;
measure a second period of time between controlling operation of the high-side FET and triggering the zero-cross detection circuit; and
adjust a third period of time based on the first period of time and the second period of time, wherein the third period of time corresponds to a dead time between controlling operation of the high-side FET and the low-side FET.
10 . The USB-PD AC-DC power supply of claim 9 , wherein the USB-PD AC-DC power supply is initially controlling the operation of the low-side FET.
11 . The USB-PD AC-DC power supply of claim 9 , wherein to trigger the zero-cross detection circuit, the secondary-side controller is further to:
determine that a respective voltage of the low-side FET or the high-side FET reaches zero.
12 . The USB-PD AC-DC power supply of claim 9 , wherein to control the operation of the low-side FET, the primary-side controller is further to:
turn off a control phase of the low-side FET.
13 . The USB-PD AC-DC power supply of claim 9 , wherein to control the operation of the high-side FET, the primary-side controller is further to:
turn off a control phase of the high-side FET.
14 . The USB-PD AC-DC power supply of claim 9 , wherein the primary-side controller is further to:
receive the third period of time from the secondary-side controller for controlling operation of the high-side FET or the low-side FET.
15 . The USB-PD AC-DC power supply of claim 9 , wherein the secondary-side controller is further to:
send the third period of time to the primary-side controller for controlling operation of the high-side FET or the low-side FET.
16 . A Universal Serial Bus Power Delivery (USB-PD) flyback converter system, the system comprising:
a flyback transformer;
an active clamp flyback (ACF) circuit;
a high-side field-effect transistor (FET) coupled between the flyback transformer and the ACF circuit;
a low-side FET coupled to the flyback transformer;
a pulse transformer;
a primary-side controller coupled to receive signals from the pulse transformer and to control operation of the high-side FET and the low-side FET; and
a secondary-side controller, wherein the secondary-side controller is to:
trigger a zero-cross detection circuit;
measure a first period of time between controlling operation of the low-side FET and triggering the zero-cross detection circuit;
measure a second period of time between controlling operation of a high-side FET and triggering the zero-cross detection circuit; and
adjust a third period of time based on the first period of time and the second period of time, wherein the third period of time corresponds to a dead time between controlling operation of the high-side FET and the low-side FET.
17 . The system of claim 16 , wherein to trigger the zero-cross detection circuit, the secondary-side controller is further to:
determine that a respective voltage of the low-side FET or the high-side FET reaches zero.
18 . The system of claim 16 , wherein to control the operation of the low-side FET, the primary-side controller is further to:
turn off a control phase of the low-side FET.
19 . The system of claim 16 , wherein to control the operation of the high-side FET, the primary-side controller is further to:
turn off a control phase of the high-side FET.
20 . The system of claim 16 , wherein the primary-side controller is further to:
receive the third period of time from the secondary-side controller for controlling operation of the high-side FET or the low-side FET.