Skew-correcting clock buffer
A method system, and apparatus for adjusting skew in a circuit comprising feeding an input clock into a first push-pull source follower stage, feeding an inverse of an input clock bar into a first CMOS inverter stage, creating an output clock based on an equal contribution of the input clock of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage, feeding the input clock bar into a first push-pull source follower stage, feeding an inverse of the input clock into a first CMOS inverter stage, and creating an output clock based on an equal contribution of the input clock bar of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage.
1. An apparatus comprising:
a Complementary Metal Oxide Semiconductor (CMOS) inverter stage;
a non-inverting push-pull source follower stage paired with the CMOS inverter stage;
a clock bar signal coupled to the non-inverting push-pull source follower stage; and
an inverse of a clock signal coupled to the CMOS inverter stage to form a clock bar out signal, wherein the clock bar signal and the inverse of the clock signal contribute equally to forming the clock bar out signal.
2. The apparatus of claim 1 , wherein the non-inverting push-pull source follower stage adjusts a skew of the clock bar signal based on a bias current in the non-inverting push-pull source follower stage.
3. The apparatus of claim 1 , wherein the CMOS inverter stage comprises a switched capacitor.
4. The apparatus of claim 3 , wherein the switched capacitor injects skew into the clock bar out signal based on a value of the switched capacitor.
5. The apparatus of claim 3 , further comprising an analog feedback loop to adjust a setting of the switched capacitor to remove clock skew.
6. The apparatus of claim 3 , further comprising a digital feedback loop to adjust a setting of the switched capacitor to remove clock skew.
7. The apparatus of claim 3 , further comprising software instructions to adjust a setting of the switched capacitor to remove clock skew.
8. An apparatus comprising:
a Complementary Metal Oxide Semiconductor (CMOS) inverter stage;
a non-inverting push-pull source follower stage paired with the CMOS inverter stage;
a clock signal coupled to the non-inverting push-pull source follower stage; and
an inverse of a clock bar signal coupled to the CMOS inverter stage to form a clock out signal, wherein the clock signal and the inverse of the clock bar signal contribute equally to forming the clock out signal.
9. The apparatus of claim 8 , wherein the non-inverting push-pull source follower stage adjusts a skew of the clock signal based on a bias current in the non-inverting push-pull source follower stage.
10. The apparatus of claim 8 , wherein the CMOS inverter stage comprises a switched capacitor.
11. The apparatus of claim 10 , wherein the switched capacitor injects skew into the clock out signal based on a value of the switched capacitor.
12. The apparatus of claim 10 , further comprising an analog feedback loop to adjust a setting of the switched capacitor to remove clock skew.
13. The apparatus of claim 10 , further comprising a digital feedback loop to adjust a setting of the switched capacitor to remove clock skew.
14. The apparatus of claim 10 , further comprising software instructions to adjust a setting of the switched capacitor to remove clock skew.
15. An apparatus comprising:
a first Complementary Metal Oxide Semiconductor (CMOS) inverter stage;
a first non-inverting push-pull source follower stage paired with the first CMOS inverter stage;
a clock bar signal coupled to the first non-inverting push-pull source follower stage;
an inverse of a clock signal coupled to the first CMOS inverter stage to form a clock bar out signal;
a second Complementary Metal Oxide Semiconductor (CMOS) inverter stage;
a second non-inverting push-pull source follower stage paired with the second CMOS inverter stage;
a second clock signal coupled to the second non-inverting push-pull source follower stage; and
an inverse of a clock bar signal coupled to the second CMOS inverter stage to combine to form a clock out signal.
16. The apparatus of claim 15 , wherein the first non-inverting push-pull source follower stage adjusts a skew of the clock bar signal based on a bias current in the first non-inverting push-pull source follower stage; and wherein the second non-inverting push-pull source follower stage adjusts the skew of the clock signal based on a bias current in the second non-inverting push-pull source follower stage.
17. The apparatus of claim 15 , wherein the first CMOS inverter stage comprises a first switched capacitor and wherein the second CMOS inverter stage comprises a second switched capacitor.
18. The apparatus of claim 17 , wherein the first switched capacitor injects skew into the clock bar out signal based on a value of the first switched capacitor.
19. The apparatus of claim 17 , wherein the second switched capacitor injects skew into the clock out signal based on a value of the second switched capacitor.
20. The apparatus of claim 17 , further comprising at least one of an analog feedback loop, a digital feedback loop, or software instructions, wherein at least one of the analog feedback loop, the digital feedback loop, or the software instructions is enabled to adjust a setting of the first switched capacitor; and wherein the at least one of the analog feedback loop, the digital feedback loop, or the software instructions is enabled to adjust a setting of the second switched capacitor to account for clock skew occurring in later circuits.