Constant on-time power converter with adjustable pulse duration and soft-start control
In accordance with an embodiment, a method for controlling a constant on-time switched mode power converter includes: generating a pulse signal having an on-time; during a soft-start phase of the power converter, successively increasing the on-time from an initial duration to a final duration, wherein the final duration is larger than the initial duration; sensing an output voltage of the power converter and generating a feedback signal proportional to the output voltage; adjusting a frequency of the pulse signal based on the feedback signal and a reference signal; and driving a power switch with the pulse signal to control the power switch and regulate the output voltage.
1 . A method for controlling a constant on-time switched mode power converter, the method comprising:
receiving, by a feedback processing circuit, a feedback signal from an output of a power converter and a reference signal from an output of a ramp signal generator;
generating, by an on-time timer coupled to an output of the feedback processing circuit, a pulse signal having an on-time duration based on a value of a signal applied to an on-time duration control port of the on-time timer;
during a soft-start phase of the power converter, successively increasing the on-time duration from an initial duration to a final duration in response to a ramped reference signal generated by a first ramp signal generator coupled to the on-time duration control port, wherein the final duration is larger than the initial duration;
sensing, by the feedback processing circuit, an output voltage of the power converter and generating the feedback signal proportional to the output voltage;
adjusting, by the feedback processing circuit, a frequency of the pulse signal based on the feedback signal and reference signal;
limiting, by a frequency limiting circuit, an output frequency of the feedback processing circuit, the frequency limiting circuit comprising an SR latch having a first input coupled to an output of the on-time timer, a second input coupled to a clock node, and an output node coupled to an input of the on-time timer; and
driving a power switch with the pulse signal to control the power switch and regulate the output voltage.
2 . The method of claim 1 , further comprising limiting a switching frequency of the pulse signal to a first switching frequency during the soft-start phase of the power converter.
3 . The method of claim 2 , wherein limiting the switching frequency of the pulse signal comprises successively decreasing an off-time between pulses of the pulse signal from a first duration to a second duration less than the first duration.
4 . The method of claim 2 , further comprising generating a trigger signal based on the feedback signal and the reference signal, wherein limiting the switching frequency of the pulse signal comprises using a clock to control a latch that gates the trigger signal for pulse generation.
5 . The method of claim 2 , wherein limiting the switching frequency of the pulse signal comprises clocking a latch having an output coupled to an input of a pulse generation circuit and an input coupled to an output of the pulse generation circuit.
6 . The method of claim 1 , further comprising generating the reference signal by increasing the reference signal from a first value to a second value during the soft-start phase of the power converter to form the ramped reference signal.
7 . The method of claim 6 , wherein generating the pulse signal comprises:
generating a ramp signal;
comparing the ramp signal with a threshold proportional to the ramped reference signal;
resetting the ramp signal when the ramp signal exceeds the threshold; and
asserting the pulse signal when the ramp signal is less than the threshold.
8 . The method of claim 7 , wherein:
generating the ramp signal comprises charging a capacitor; and
resetting the ramp signal comprises turning on a switch coupled between a first terminal and a second terminal of the capacitor.
9 . The method of claim 1 , wherein successively increasing the on-time duration from the initial duration to the final duration decreases output current spikes during the soft-start phase of the power converter.
10 . The method of claim 1 , further comprising maintaining the on-time duration at the final duration during a normal operation phase of the power converter.
11 . The method of claim 1 , wherein successively increasing the on-time duration from the initial duration to the final duration is only performed during the soft-start phase of the power converter.
12 . A switched-mode power converter comprising:
a feedback processing circuit having an input coupled to an output node of the switched-mode power converter;
an on-time timer coupled to an output of the feedback processing circuit, the on-time timer configured to produce a pulse having an on-time duration based on a value of a signal applied to an on-time duration control port;
a frequency limiting circuit comprising an SR latch having a first input coupled to an output of the on-time timer, a second input coupled to a clock node, and an output node coupled to an input of the on-time timer, wherein the frequency limiting circuit is configured to limit an output frequency of the on-time timer; and
a first ramp signal generator having an output coupled to the on-time duration control port, the first ramp signal generator configured to produce a ramped reference signal during a soft-start phase of the switched-mode power converter and a substantially constant reference signal during a normal operation of the switched-mode power converter.
13 . The switched-mode power converter of claim 12 , wherein:
the frequency limiting circuit comprises an off-time timer having an input coupled to an output of the on-time timer and an output coupled to an input of the on-time timer; and
the off-time timer is configured to produce a second pulse having a duration based on the value of the signal applied to a duration control port of the off-time timer, wherein the signal applied to the duration control port of the off-time timer is an output of the first ramp signal generator.
14 . The switched-mode power converter of claim 13 , wherein the off-time timer comprises:
a first voltage controlled current source having a control node coupled to the output of the first ramp signal generator;
a first capacitor coupled to the first voltage controlled current source;
a first switch having a load path coupled across the first capacitor and a control node coupled to an output of the on-time timer; and
a first comparator having a first input coupled to the first capacitor and a second input coupled to a fixed reference voltage node.
15 . The switched-mode power converter of claim 12 , further comprising:
a driver circuit having an input coupled to an output of the on-time timer; and
a switching circuit coupled between an input node and the output node of the switched-mode power converter.
16 . The switched-mode power converter of claim 15 , wherein the switching circuit comprises a MOS half-bridge circuit.
17 . The switched-mode power converter of claim 12 , wherein the feedback processing circuit comprises:
an error amplifier having a first input coupled to the output node of the switched-mode power converter, and a second input coupled to an output of the first ramp signal generator;
a second ramp signal generator; and
a comparator having a first input configured to receive a sum of an output of the error amplifier and an output of the second ramp signal generator, and a second input coupled to the output node of the switched-mode power converter.
18 . A switched-mode power converter comprising:
a reference signal generator configured to produce a ramped reference signal during a soft-start phase of the switched-mode power converter and a substantially constant reference signal during a normal operation of the switched-mode power converter;
a half-bridge circuit having an input coupled to a power supply input node and an output coupled to an output of the switched-mode power converter;
a gate driver coupled to a control input of the half-bridge circuit;
a feedback processing circuit comprising a ramp signal generator, an error amplifier having a first input coupled to the output of the switched-mode power converter and a second input coupled to an output of the reference signal generator, and a comparator having a first input configured to receive a sum of an output of the error amplifier and an output of the ramp signal generator, the comparator having a second input coupled to an output node of the switched-mode power converter, the feedback processing circuit configured to produce a trigger signal having a frequency based on input signals at the first input and the second input of the error amplifier; and
a first pulse generator coupled to an output of the feedback processing circuit, the first pulse generator configured to produce a pulse having an on-time duration based on a value of the signal at the output of the reference signal generator.
19 . The switched-mode power converter of claim 18 , further comprising a frequency limiter comprising an off-time timer having an input coupled to an output of the first pulse generator and an output coupled to an input of the first pulse generator, the off-time timer configured to produce the pulse.
20 . The switched-mode power converter of claim 19 , wherein the frequency limiter comprises a second pulse generator configured to produce a second pulse having a pulse width inversely proportional to the signal at the output of the reference signal generator.
21 . The switched-mode power converter of claim 18 , further comprising an inductor coupled between the output of the half-bridge circuit and the output of the switched-mode power converter.
22 . The switched-mode power converter of claim 18 , further comprising an on-time timer coupled to an output of the feedback processing circuit, the on-time timer configured to produce the pulse with the on-time duration based on a value of a signal applied to an on-time duration control port.
23 . The switched-mode power converter of claim 18 , wherein during the soft-start phase, the on-time duration is successively increased from an initial duration to a final duration corresponding to the ramped reference signal coupled to an on-time duration control port, wherein the final duration is larger than the initial duration.