METHOD AND APPARATUS RELATED TO CONTROLLABLE THIN FILM RESISTORS FOR ANALOG INTEGRATED CIRCUITS
An integrated circuit die includes a silicon chromium (SiCr) thin film resistor disposed on a first oxide layer. The SiCr thin film resistor has a resistor body and a resistor head. A second oxide layer overlays the SiCr thin film resistor. The second oxide layer has an opening exposing a surface of the resistor head. A metal pad is disposed in the opening in the second oxide layer and is contact with the surface of the resistor head exposed by the opening. Further, an interlevel dielectric layer is disposed on the second oxide layer overlaying the SiCr thin film resistor. A metal-filled via extends from a top surface of interlevel dielectric layer through the interlevel dielectric layer and contacts the metal pad disposed in the opening in the second oxide layer.
1 . (canceled)
2 . An integrated circuit die comprising:
an interlevel dielectric layer disposed on a substrate;
a silicon chromium (SiCr) thin film resistor disposed in the interlevel dielectric layer; and
a metal-filled via extending from a top surface of interlevel dielectric layer toward the substrate into the SiCr thin film resistor with a metal disposed in the metal-filled via being in direct contact with the SiCr thin film resistor.
3 . The integrated circuit die of claim 2 , wherein the metal disposed in the metal-filled via contacts the SiCr thin film resistor through a sidewall of the metal-filled via.
4 . The integrated circuit die of claim 2 , wherein the metal-filled via punches through the SiCr thin film resistor.
5 . The integrated circuit die of claim 4 , wherein the metal-filled via terminates at a landing pad disposed below the SiCr thin film resistor.
6 . The integrated circuit die of claim 5 , wherein the landing pad is aligned with and disposed below a resistor head of the SiCr thin film resistor, and wherein the metal-filled via punches through the resistor head and contacts the resistor head through a sidewall of the metal-filled via.
7 . The integrated circuit die of claim 4 , wherein the metal-filled via terminates at a bottom surface of the SiCr thin film resistor.
8 . The integrated circuit die of claim 2 , wherein the SiCr thin film resistor has a thickness in a range of about 40 angstroms to about 100 angstroms.
9 . The integrated circuit die of claim 2 , wherein the SiCr thin film resistor comprises an amorphous silicon-chromium thin film with a weight % of Cr between 40% and 60 % and a weight % of C between 0% and 15%.
10 . The integrated circuit die of claim 2 , wherein the SiCr thin film resistor is disposed on an oxide layer, a protective dielectric layer overlays the SiCr thin film resistor, and a portion of interlevel dielectric layer is disposed on the protective dielectric layer overlaying the SiCr thin film resistor.
11 . The integrated circuit die of claim 10 , wherein the protective dielectric layer is a silicon nitride layer having a thickness in a range of about 200 angstroms to about 800 angstroms.
12 . The integrated circuit die of claim 2 , wherein the metal-filled via includes tungsten metal.
13 . An integrated circuit die comprising:
a silicon chromium (SiCr) thin film resistor disposed on a first oxide layer on a substrate, the SiCr thin film resistor having a resistor body and a resistor head;
an interlevel dielectric layer disposed on a protective dielectric layer overlaying the SiCr thin film resistor; and
a metal-filled via extending from a top surface of interlevel dielectric layer through the interlevel dielectric layer and the protective dielectric layer into the resistor head of SiCr thin film resistor, the metal-filled via terminating at a landing pad disposed below the SiCr thin film resistor in the die.
14 . The integrated circuit die of claim 13 , wherein the SiCr thin film resistor has a thickness in a range of about 40 angstroms to about 100 angstroms.
15 . The integrated circuit die of claim 13 , wherein the landing pad includes metal or metallic material.
16 . The integrated circuit die of claim 13 , wherein the landing pad is aligned with and disposed below the resistor head of the SiCr thin film resistor, and a metal disposed in the metal-filled via is in direct contact with the resistor head of the SiCr thin film resistor.
17 . The integrated circuit die of claim 13 , wherein the resistor head of the SiCr thin film resistor is disposed on a top surface of the landing pad, and wherein the metal-filled via punches through the SiCr thin film resistor and contacts the resistor head through a sidewall of the metal-filled via.
18 . An integrated circuit die comprising:
an interlevel dielectric (ILD) layer disposed on a substrate, the ILD layer including:
a silicon chromium (SiCr) thin film resistor having a resistor body and a resistor head;
a landing pad disposed under and in contact with the resistor head of the SiCr thin film resistor; and
a metal-filled via extending from a top surface of the ILD layer through the ILD layer to contact the landing pad disposed under the resistor head.
19 . The integrated circuit die of claim 18 , wherein the landing pad has a block shape with at least a side and a top surface and wherein the SiCr thin film resistor is a thin film sputtered on the side and the top surface of the landing pad.
20 . The integrated circuit die of claim 19 , wherein the landing pad is made of metal or metallic materials.
21 . The integrated circuit die of claim 19 , wherein electrical contact to (SiCr) thin film resistor is established through a sidewall of the metal-filled via and along an interface between the landing pad and the thin film sputtered on the side and the top surface of the landing pad.