OPTIMIZATION OF DATA ACCESS AND COMMUNICATION IN MEMORY SYSTEMS
A memory system having one or more memory components and a controller. The controller can receive access requests from a communication connection. The access requests can identify data items associated with the access requests, addresses of the data items, and contexts of the data items in which the data items are used for the access requests. The controller can identify separate memory regions for separate contexts respectively, determine placements of the data items in the separate memory regions based on the contexts of the data items, and determine a mapping between the addresses of the data items and memory locations that are within the separate memory regions corresponding to the contexts of the data items. The memory system stores store the data items at the memory locations separated by different memory regions according to different contexts.
1 . A memory system, comprising:
one or more memory components; and
a processing device, operatively coupled with the one or more memory components, to at least:
receive, from a host system, first access requests;
receive, from the host system, information identifying contexts of the first access requests;
generate second access requests in accordance with the first access request; and
transmit the second access requests to the one or more memory components.
2 . The memory system of claim 1 , wherein the processing device is further configured to:
generate different tags to represent different contexts; and
wherein the second access request include the different tags representing the contexts of the first access requests.
3 . The memory system of claim 1 , wherein the second access requests are transmitted via one or more serial connection to the one or more memory components respectively.
4 . The memory system of claim 1 , wherein the processing device is further configured to combine a subset of the first access requests as a single access request transmitted to a memory component.
5 . The memory system of claim 3 , wherein the subset of the first access requests includes read requests.
6 . The memory system of claim 3 , wherein the subset of the first access requests includes requests of a same type.
7 . The memory system of claim 3 , wherein the processing device is further configured to receive a response to the single access request and generate a plurality of responses for the subset of the first access requests respectively from the response to the single access request.
8 . The memory system of claim 3 , wherein the second access requests in accordance with a standard for serial advanced technology attachment (SATA), peripheral component interconnect express (PCIe), or universal serial bus (USB).
9 . A method comprising:
receiving, via a processing device operatively coupled with the one or more memory components, first access requests from a host system;
receiving, via the processing device, information identifying contexts of the first access requests from the host system;
generating, via the processing device, second access requests in accordance with the first access request; and
transmitting, via the processing device, the second access requests to the one or more memory components.
10 . The method of claim 9 , further comprising
generating, via the processing device, different tags to represent different contexts; and
wherein the second access request include the different tags representing the contexts of the first access requests.
11 . The method of claim 9 , wherein the second access requests are transmitted via one or more serial connection to the one or more memory components respectively.
12 . The method of claim 9 , further comprising:
combining, via the processing device, a subset of the first access requests as a single access request transmitted to a memory component.
13 . The method of claim 11 , wherein the subset of the first access requests includes read requests.
14 . The method of claim 11 , wherein the subset of the first access requests includes requests of a same type.
15 . The method of claim 11 , further comprising:
receiving, via the processing device, a response to the single access request and generate a plurality of responses for the subset of the first access requests respectively from the response to the single access request.
16 . The method of claim 11 , wherein the second access requests in accordance with a standard for serial advanced technology attachment (SATA), peripheral component interconnect express (PCIe), or universal serial bus (USB).
17 . A computer readable medium having stored thereon a set of instructions, which when executed cause a processing to device to perform a method comprising:
receiving, via the processing device operatively coupled with the one or more memory components, first access requests from a host system;
receiving, via the processing device, information identifying contexts of the first access requests from the host system;
generating, via the processing device, second access requests in accordance with the first access request; and
transmitting, via the processing device, the second access requests to the one or more memory components.
18 . The computer readable medium of claim 17 , wherein the instructions which when executed cause the processor to perform the method further comprising:
generating, via the processing device, different tags to represent different contexts; and
wherein the second access request include the different tags representing the contexts of the first access requests.
19 . The computer readable medium of claim 17 , wherein the second access requests are transmitted via one or more serial connection to the one or more memory components respectively.
20 . The computer readable medium of claim 17 , wherein the instructions which when executed cause the processor to perform the method further comprising:
combining, via the processing device, a subset of the first access requests as a single access request transmitted to a memory component.