NSN detection in primary-side-controlled AC-DC converter
An AC-DC converter and method of operating the same is provided to sense negative voltage (NSN) on a synchronous rectifier (SR_DRAIN) on a secondary-side of the converter. The SR_DRAIN voltage is sensed and a first integration signal (volt-sec) generated based on a time and voltage for which the SR_DRAIN voltage is greater than a bus voltage (V BUS_IN ) output from the secondary. When Volt-sec is greater than a reference voltage a volt-sec based NSN detect signal is generated. A second integration signal (integ_resetb) is generated based on the time for which the SR_DRAIN voltage is greater than V BUS_IN . A pulse width of integ_resetb is determined using a counter, and, when it exceeds a reference by a predetermined percentage, a counter-expiry signal is generated. The volt-sec based NSN detect signal and the counter-expiry signal are logically combined to generate a real NSN detect signal when one or both are present.
1. A method of operating an AC-DC converter, the method comprising:
sensing on a drain node of a synchronous rectifier (SR) on a secondary-side of the AC-DC converter a SR_DRAIN voltage greater than a bus voltage (V BUS_IN ) output from the AC-DC converter;
generating a first integration (volt-sec) signal based on a time and voltage for which the SR_DRAIN voltage is greater than V BUS_IN ;
generating a second integration (integ_resetb) signal having a pulse width based on the time for which the SR_DRAIN voltage is greater than V BUS_IN output from the secondary-side of the AC-DC converter;
comparing the volt-sec to a reference voltage (Vref), and when volt-sec is greater than Vref, generating a volt-sec based negative voltage sensed (NSN) detect signal;
determining the pulse width of the integ_resetb signal using a counter and when pulse width exceeds a reference pulse width by greater than a predetermined percentage, generating a counter-expiry signal; and
logically combining the volt-sec based NSN detect signal and the counter-expiry signal to generate a combined NSN detect signal when one or both of the volt-sec based NSN detect signal and the counter-expiry signal are present.
2. The method of claim 1 , further comprising coupling the combined NSN detect signal to a SR gate driver to turn on the SR.
3. The method of claim 2 wherein turning on the SR due to the SR_DRAIN voltage dropping to a negative voltage followed by a gradual rise in SR_DRAIN voltage, and further comprising turning off the SR when a rising SR_DRAIN voltage crosses zero volts.
4. The method of claim 3 further comprising cycling a power switch (PS) in a primary-side of the AC-DC converter on and off to couple an input line voltage to a primary-winding of a transformer in the AC-DC,
wherein the SR_DRAIN voltage is received when the power switch is on, and
wherein after turning off the SR, when both the PS and the SR are off an inductor-capacitor (LC) circuit formed by the primary-winding, PS and a snubber in the primary-side generates an LC ringing in the SR_DRAIN voltage.
5. The method of claim 4 wherein Vref is selected so that the volt-sec generated by integration of the SR_DRAIN voltage in response to the LC ringing is less than Vref and the volt-sec based NSN detect signal is not generated.
6. The method of claim 4 wherein the reference pulse width is selected so that the pulse width of the integ_resetb signal generated in response to the LC ringing of the SR_DRAIN voltage less than reference pulse width, and the counter-expiry signal and resultant NSN detect signal are not generated.
7. The method of claim 4 wherein when the transformer has a high primary-to-secondary turn-ratio and the input line voltage is low, the SR_DRAIN voltage is clipped so that the volt-sec based NSN detect signal is not generated, and the pulse width of the integ_resetb signal exceeds the reference pulse width by greater than the predetermined percentage, generating the counter-expiry signal and the combined NSN detect signal.
8. A method of operating an AC-DC converter comprising:
sensing on a drain node of a synchronous rectifier (SR) on a secondary-side of the AC-DC converter a SR_DRAIN voltage greater than a bus voltage (V BUS_IN ) output from the AC-DC converter;
integrating the SR_DRAIN voltage to generate a volt-sec signal based on a time and voltage for which the SR_DRAIN voltage is greater than V BUS_IN ;
generating an integration reset bar signal (integ_resetb) having a pulse width based on the time for which the SR_DRAIN voltage is greater than V BUS_IN ;
determining the pulse width of the integ_resetb signal using a counter, and, when the pulse width exceeds a reference pulse width by greater than a predetermined percentage, generating a counter-expiry signal; and
generating and coupling a negative voltage sensed (NSN) detect signal to a SR gate driver to turn on the SR when the counter-expiry signal is present.
9. The method of claim 8 , further comprising comparing the volt-sec to a reference voltage (Vref), and when volt-sec is greater than Vref, generating a volt-sec based NSN detect signal, and wherein generating and coupling the NSN detect signal to the SR gate driver comprises logically combining the volt-sec based NSN detect signal with the counter-expiry signal, and generating and coupling the NSN detect signal to the SR gate driver when one or both of the volt-sec based NSN detect signal and the counter-expiry signal are present.
10. The method of claim 9 wherein turning on the SR due to the SR_DRAIN voltage dropping to a negative voltage followed by a gradual rise in SR_DRAIN voltage, and further comprising turning off the SR when the SR_DRAIN voltage crosses zero volts.
11. The method of claim 10 further comprising cycling a power switch (PS) in a primary-side of the AC-DC converter on and off to couple an input line voltage to a primary-winding of a transformer in the AC-DC, wherein the SR_DRAIN voltage is received when the power switch is on, and wherein after turning off the SR, when both the PS and the SR are off an inductor-capacitor (LC) circuit formed by the primary-winding, PS and a snubber in the primary-side produces an LC ringing in the SR_DRAIN voltage.
12. The method of claim 11 wherein Vref is selected so that the volt-sec generated by integration of the SR_DRAIN voltage in response to the LC ringing is less than Vref and the volt-sec based NSN detect signal is not generated.
13. The method of claim 11 wherein the reference pulse width is selected so that the pulse width of the integ_resetb signal generated in response to the LC ringing of the SR_DRAIN voltage less than reference pulse width, and the counter-expiry signal and resultant NSN detect signal are not generated.
14. The method of claim 11 wherein when the transformer has a high primary-to-secondary turn-ratio and the input line voltage is low, the SR_DRAIN voltage is clipped so that the volt-sec based NSN detect signal is not generated, and the pulse width of the integ_resetb signal exceeds the reference pulse width by greater than the predetermined percentage, generating the counter-expiry signal and the NSN detect signal.
15. An AC-DC converter comprising:
a transformer including a primary-winding coupled to a rectified AC input line voltage through a power switch (PS) and a secondary-winding coupled to a DC output and to a ground terminal through a synchronous rectifier (SR), the SR having a drain node (SR_DRAIN) coupled to the secondary-winding and a source node coupled to the ground terminal, wherein the DC output provides a bus voltage (V BUS_IN ) output;
a primary-controller coupled to control the PS; and
a SR-controller coupled to control the SR, wherein the SR-controller is operable to:
generate a first integration (volt-sec) signal based on a time and voltage for which a SR_DRAIN voltage is greater than V BUS_IN ;
generate a second integration (integ_resetb) signal based on the time for which the SR_DRAIN voltage is greater than V BUS_IN output from a secondary-side of the AC-DC converter;
compare the volt-sec to a reference voltage (Vref), and when volt-sec is greater than Vref, generate a volt-sec based negative voltage sensed (NSN) detect signal;
determine a pulse width of the integ_resetb signal using a counter and when pulse width exceeds a reference pulse width by greater than a predetermined percentage, generate a counter-expiry signal; and
logically combine the volt-sec based NSN detect signal and the counter-expiry signal to generate a combined NSN detect signal when one or both of the volt-sec based NSN detect signal and the counter-expiry signal are present.
16. The AC-DC converter of claim 15 , wherein the SR-controller further comprises a SR gate driver to turn on and off the SR, and wherein the SR-controller is operable to couple the combined NSN detect signal to the SR gate driver to turn on the SR.
17. The AC-DC converter of claim 16 , wherein after turning off the SR, when both the PS and the SR are off an inductor-capacitor (LC) circuit formed by the primary-winding, PS and a snubber in a primary-side of the AC-DC converter produces an LC ringing in the SR_DRAIN voltage, and wherein Vref is selected so that the volt-sec generated by integration of the SR_DRAIN voltage in response to the LC ringing is less than Vref and the volt-sec based NSN detect signal is not generated.
18. The AC-DC converter of claim 15 , wherein the transformer has a high primary-to-secondary turn-ratio so that when the rectified AC input is low the SR_DRAIN voltage is clipped and the volt-sec based NSN detect signal is not generated, and the SR-controller is operable so that the pulse width of the integ_resetb signal exceeds the reference pulse width by greater than the predetermined percentage, generating the counter-expiry signal and the combined NSN detect signal.
19. The AC-DC converter of claim 15 , wherein the AC-DC converter is compliant with a Universal Serial Bus Power Delivery (USB-PD) specification.
20. The AC-DC converter of claim 15 , further comprising a Universal Serial Bus Type-C (USB-C) connector coupled to the DC output to receive the V BUS_OUT voltage.