IP Library Patent Application 18363149
Patent Application
App. No. 18/363,149

METHODS FOR IMPROVING PASSIVATION LAYER DURABILITY

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Quick Facts
Patent No.
US None
App. No.
18/363,149
Abstract

Methods, systems, and devices for improving passivation layer durability are described. A device may include a semiconductor substrate elongated along a first direction and a second direction. The first direction may be parallel to a width of the semiconductor substrate and the second direction may be parallel to a depth of the semiconductor substrate. The device may include one or more layers formed above the semiconductor substrate with respect to a third direction parallel to a height of the semiconductor substrate. At least a region of the one or more layers may include circuitry. The device may include a passivation layer formed above the one or more layers with respect to the third direction. The passivation layer may include a plurality of cavities that each extend through the passivation layer. The plurality of cavities and the circuitry may be non-overlapping with respect to the first direction and the second direction.

Claims (41)

1 . An apparatus, comprising:

a semiconductor substrate elongated along a first direction and a second direction, the first direction parallel to a width of the semiconductor substrate and the second direction parallel to a depth of the semiconductor substrate;

one or more layers formed above the semiconductor substrate with respect to a third direction parallel to a height of the semiconductor substrate, wherein at least a region of the one or more layers comprises circuitry; and

a passivation layer formed above the one or more layers with respect to the third direction, the passivation layer comprising a plurality of cavities that each extend through the passivation layer, wherein the plurality of cavities and the circuitry are non-overlapping with respect to the first direction and the second direction.

2 . The apparatus of claim 1 , wherein the one or more layers comprise:

an insulating layer formed between the circuitry and the passivation layer, wherein each cavity of the plurality of cavities exposes a surface of the insulating layer.

3 . The apparatus of claim 1 , wherein each cavity of the plurality of cavities is formed in a shape of an elliptical cylinder comprising a height axis parallel to the third direction.

4 . The apparatus of claim 3 , wherein a ratio between a major axis and a minor axis of each elliptical cylinder is 3 to 1.

5 . The apparatus of claim 1 , wherein the plurality of cavities are arranged in a rectangular pattern comprising uniform spacing between each cavity of the plurality of cavities.

6 . The apparatus of claim 1 , wherein the semiconductor substrate comprises a silicon carbide material.

7 . The apparatus of claim 1 , wherein the one or more layers comprise:

a silicon carbide layer formed in contact with the semiconductor substrate;

a metal layer formed at least partially in contact with the silicon carbide layer; and

a silicon nitride layer formed at least partially in contact with the metal layer.

8 . The apparatus of claim 1 , wherein the circuitry comprises transistor circuitry.

9 . A method, comprising:

forming a semiconductor substrate elongated along a first direction and a second direction, the first direction parallel to a width of the semiconductor substrate and the second direction parallel to a depth of the semiconductor substrate;

forming one or more layers above the semiconductor substrate with respect to a third direction parallel to a height of the semiconductor substrate, wherein at least a region of the one or more layers comprises circuitry; and

forming a passivation layer above the one or more layers with respect to the third direction, the passivation layer comprising a plurality of cavities that each extend through the passivation layer, wherein the plurality of cavities and the circuitry are non-overlapping with respect to the first direction and the second direction.

10 . The method of claim 9 , wherein forming the one or more layers comprises:

forming an insulating layer between the circuitry and the passivation layer, wherein each cavity of the plurality of cavities exposes a surface of the insulating layer.

11 . The method of claim 9 , wherein forming each cavity of the plurality of cavities comprises:

forming a cavity in a shape of an elliptical cylinder comprising a height axis parallel to the third direction.

12 . The method of claim 11 , wherein a ratio between a major axis and a minor axis of each elliptical cylinder is 3 to 1.

13 . The method of claim 9 , wherein the plurality of cavities are arranged in a rectangular pattern comprising uniform spacing between each cavity of the plurality of cavities.

14 . The method of claim 9 , wherein forming the semiconductor substrate comprises:

forming the semiconductor substrate using a silicon carbide material.

15 . The method of claim 9 , wherein forming the one or more layers comprises:

forming a silicon carbide layer in contact with the semiconductor substrate;

forming a metal layer at least partially in contact with the silicon carbide layer; and

forming a silicon nitride layer at least partially in contact with the metal layer.

16 . A product formed by a method, comprising:

forming a semiconductor substrate elongated along a first direction and a second direction, the first direction parallel to a width of the semiconductor substrate and the second direction parallel to a depth of the semiconductor substrate;

forming one or more layers above the semiconductor substrate with respect to a third direction parallel to a height of the semiconductor substrate, wherein at least a region of the one or more layers comprises circuitry; and

forming a passivation layer above the one or more layers with respect to the third direction, the passivation layer comprising a plurality of cavities that each extend through the passivation layer, wherein the plurality of cavities and the circuitry are non-overlapping with respect to the first direction and the second direction.

17 . The product formed by the method of claim 16 , wherein forming the one or more layers comprises:

forming an insulating layer between the circuitry and the passivation layer, wherein each cavity of the plurality of cavities exposes a surface of the insulating layer.

18 . The product formed by the method of claim 16 , wherein forming each cavity of the plurality of cavities comprises:

forming a cavity in a shape of an elliptical cylinder comprising a height axis parallel to the third direction.

19 . The product formed by the method of claim 18 , wherein a ratio between a major axis and a minor axis of each elliptical cylinder is 3 to 1.

20 . The product formed by the method of claim 16 , wherein the plurality of cavities are arranged in a rectangular pattern comprising uniform spacing between each cavity of the plurality of cavities.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2024
From: STMICROELECTRONICS S.R.L.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 068434/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2023
From: BELLOCCHI, GABRIELE; RASCUNA', SIMONE; TORRISI, GIACOMO
To: STMICROELECTRONICS S.R.L.
Reel/Frame 064449/0452 →