IP Library Granted Patent US 12,562,769
Granted Patent B2
US 12,562,769 · App. 18/363,243 · Granted Feb 24, 2026

Integrated wideband communication circuit

Inventors: Douglas S. Jansen (Durango, CO); Sean Sengele (Groton, MA); Marc A. Fisher (Amherst, NH); Gregory M. Flewelling (Freeport, ME); Curtis M. Grens (Manchester, NH)
Assignee: BAE Systems Information and Electronic Systems Integration Inc.
H04B1/3805H04B1/0483H04B2001/3811
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Quick Facts
Patent No.
US 12,562,769
App. No.
18/363,243
Granted
Feb 24, 2026
Kind
B2
Abstract

A communications circuit includes a first circuit block and a second circuit block. The first circuit block includes a first splitter, a first signal path coupled to a first output of the first splitter, a second signal path coupled to a second output of the first splitter, and a first switch configured to couple the second signal path to a third signal path or to couple a fourth signal path to the third signal path. The second circuit block includes a second splitter, a fifth signal path coupled to a first output of the second splitter, a sixth signal path coupled to a second output of the second splitter, and a second switch configured to couple the sixth signal path to the third signal path or to couple a seventh signal path to the third signal path. The third signal path extends between the first and second circuit blocks.

Claims (22)

1 . A communications circuit, comprising:

a first circuit block, comprising:

a first splitter configured to receive a first local oscillator signal from a first local oscillator,

a first signal path coupled to a first output of the first splitter,

a second signal path coupled to a second output of the first splitter,

a first switch configured to couple the second signal path to a third signal path or to couple a fourth signal path to the third signal path, and

a first multiplexer having a first input coupled to the first signal path and a second input coupled to the fourth signal path; and

a second circuit block, comprising:

a second splitter configured to receive a second local oscillator signal from a second local oscillator;

a fifth signal path coupled to a first output of the second splitter;

a sixth signal path coupled to a second output of the second splitter;

a second switch configured to couple the sixth signal path to the third signal path or to couple a seventh signal path to the third signal path; and

a second multiplexer having a first input coupled to the fifth signal path and a second input coupled to the seventh signal path;

wherein the third signal path extends between the first circuit block and the second circuit block.

2 . The communications circuit of claim 1 , wherein one or more outputs of the first multiplexer are coupled to one or more frequency multiplier circuits.

3 . The communications circuit of claim 2 , wherein one or more outputs of the one or more frequency multiplier circuits are coupled to one or more inputs of a third multiplexer.

4 . The communications circuit of claim 3 , wherein one or more outputs of the third multiplexer are coupled to one or more mixers configured to mix signals on the one or more outputs of the third multiplexer with one or more received RF signals.

5 . The communications circuit of claim 1 , wherein the first circuit block is on a first semiconductor die and the second circuit block is on a second semiconductor die.

6 . The communications circuit of claim 5 , wherein the first semiconductor die and the second semiconductor die are located within a same integrated circuit package.

7 . The communications circuit of claim 5 , wherein the first semiconductor die is on a first printed circuit board and the second semiconductor die is on a second printed circuit board.

8 . The communications circuit of claim 1 , wherein the first circuit block further comprises a first amplifier on the fourth signal path and the second circuit block further comprises a second amplifier on the seventh signal path.

9 . An integrated circuit including the communications circuit of claim 1 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2023
From: JANSEN, DOUGLAS S.; SENGELE, SEAN; FISHER, MARC A.; FLEWELLING, GREGORY M.; GRENS, CURTIS M.
To: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.
Reel/Frame 064453/0091 →
Continuity (1)
Related Publication 20250047315A1 · Feb 6, 2025
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