INTEGRATED CIRCUIT WITH I/O PAD CLUSTERS AND ESD ROUTING

1 . A device, comprising:

an integrated circuit die including:

core circuitry implemented in one or more layers of semiconductor material;

a first cluster of first contact pads formed of a top metal layer of the integrated circuit die and coupled to the core circuitry;

a second cluster of second contact pads formed of the top metal layer and coupled to the core circuitry;

a first ESD protection line formed of the top metal layer extending between an area of the first cluster and an area of the second cluster; and

ESD protection circuitry in the one or more layers of semiconductor material coupling each of the first contact pads and each of the second contact pads to the first ESD protection line by ESD protection circuitry;

a passivation layer on the integrated circuit die; and

a second ESD protection line on the passivation layer formed of a redistribution metal layer and shorting a portion of the first ESD protection line.

2 . The device of claim 1 , comprising solder balls electrically balls each electrically coupled to one of the first contact pads or the second contact pads.

3 . The device of claim 1 , comprising a third ESD protection line formed of the redistribution metal layer, wherein the integrated circuit die includes:

a third cluster of third contact pads formed of the top metal layer; and

an ESD connection line formed of the top metal layer and electrically coupling the third ESD protection line to the second ESD protection line, wherein the third ESD protection line is coupled to each of the third contact pads by the ESD protection circuitry.

4 . The device of claim 1 , wherein the ESD protection circuitry includes diodes.

5 . The device of claim 1 , wherein the first ESD protection line is coupled to ground.

6 . The device of claim 1 , wherein the second ESD protection line is coupled to the first ESD protection line at a first location by a first opening in the passivation layer and at a second location via a second opening in the passivation layer.

7 . The device of claim 1 , wherein the second ESD protection line has lower resistance between the first cluster and the second cluster than does the first ESD protection line.

8 . The device of claim 1 , wherein the top metal layer includes aluminum and the redistribution metal layer includes copper.

9 . The device of claim 1 , wherein the integrated circuit includes:

a plurality of third contact pads formed of the top metal layer and positioned adjacent to an edge of the integrated circuit die; and

a ground ring below the third contact pads.

10 . The device of claim 9 , wherein the first and second clusters are further from the edge than are the contact pads.

11 . The device of claim 1 , wherein the core circuitry includes transistors.

12 . A method, comprising:

forming a plurality of metal layers of an integrated circuit die above a semiconductor substrate of the integrated circuit die, the plurality of layers including a top metal layer;

forming, from the top metal layer, a first cluster of first contact pads, a second cluster of second contact pads, and a first ESD protection line coupled to each of the first and second contact pads via ESD protection circuitry;

forming a passivation layer on the first ESD protection line; and

forming, from a redistribution metal layer on the passivation layer, a second ESD protection line electrically coupled to the first ESD protection line via a first opening in the passivation layer adjacent to the first cluster and via a second opening in the passivation layer adjacent to the second cluster.

13 . The method of claim 12 , comprising forming the top metal layer during a wafer processing stage.

14 . The method of claim 13 , comprising forming the redistribution metal layer during a packaging stage.

15 . The method of claim 12 , comprising:

forming, from the top metal layer, an ESD connection line; and

forming, from the redistribution metal layer, a third ESD protection line electrically coupled to the second ESD protection line by the ESD connection line.

16 . The method of claim 12 , wherein the first ESD protection line has a higher resistance between the first and second clusters than does the second ESD protection line.

17 . The method of claim 16 , wherein the first top metal layer includes aluminum and the redistribution metal layer includes copper.

18 . A method, comprising:

forming, from a top metal layer of an integrated circuit die:

a first cluster of first interior contact pads adjacent to each other;

a second cluster of second interior contact pads adjacent to each other;

a plurality of peripheral contact pads adjacent to an edge of the integrated circuit die;

a first ESD protection line extending between the first cluster and the second cluster and electrically coupled to each of the first and second interior contact pads by ESD protection circuitry;

forming, from a redistribution metal layer over the top metal layer, a second ESD protection line shorting out at least a portion of the first ESD protection line; and

forming a plurality of solder connection structures each coupled to a respective first interior contact pad, a second interior contact pad, or a peripheral contact pad by portions of the redistribution metal layer.

19 . The method of claim 18 , wherein the first ESD protection line has a higher resistance between the first and second clusters than does the second ESD protection line.

20 . The method of claim 19 , wherein the first top metal layer includes aluminum and the redistribution metal layer includes copper.