IP Library Granted Patent US 12,401,451
Granted Patent B2
US 12,401,451 · App. 18/367,937 · Granted Aug 26, 2025

Signal processing

Inventor: George Varghese (Hyderabad, IN)
Assignee: Nordic Semiconductor ASA
H04L1/0054H04L27/2649
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Quick Facts
Patent No.
US 12,401,451
App. No.
18/367,937
Granted
Aug 26, 2025
Kind
B2
Abstract

A receiver apparatus is configured to receive a radio-frequency signal comprising a first subcarrier comprising first subcarrier symbols and a second subcarrier comprising second subcarrier symbols, wherein the first subcarrier symbols and the second subcarrier symbols both encode a same bit sequence in a respective first subcarrier symbol and a second subcarrier symbol. Soft-output decoder logic calculates respective log-likelihood ratios for each of the first subcarrier symbols and generates a first output sequence comprising the respective log-likelihood ratios calculated for the first subcarrier symbols and similarly generates a second output sequence. Combiner logic combines the output sequences by adding or subtracting a respective log-likelihood ratio with a respective log-likelihood ratio calculated for the respective second subcarrier symbol to obtain a combined log-likelihood ratio for a respective bit of the bit sequence, and outputs a combined output sequence comprising a respective combined log-likelihood ratio for each bit of the bit sequence.

Claims (81)

1. A receiver apparatus comprising:

receiving circuitry configured to receive a radio-frequency signal comprising a first subcarrier comprising first subcarrier symbols and a second subcarrier comprising second subcarrier symbols, wherein the first subcarrier symbols and the second subcarrier symbols both encode a same bit sequence, the bit sequence comprising sets of one or more bits, wherein a respective set of one or more bits is encoded in a respective first subcarrier symbol of the first subcarrier and also in a respective second subcarrier symbol of the second subcarrier, the first subcarrier symbol and second subcarrier symbol occupying a same respective symbol period, and wherein the first and second subcarriers have a same type of modulation and different subcarrier frequencies; and

soft-output decoder logic and combiner logic, each comprising respective circuitry or comprising respective software instructions stored in a memory of the receiver apparatus for execution by a processor of the receiver apparatus,

wherein the soft-output decoder logic is configured to:

calculate one or more respective log-likelihood ratios for each of the first subcarrier symbols and generate a first output sequence comprising the respective log-likelihood ratios calculated for the first subcarrier symbols; and

calculate one or more respective log-likelihood ratios for each of the second subcarrier symbols and generate a second output sequence comprising the respective log-likelihood ratios calculated for the second subcarrier symbols;

wherein the combiner logic is configured to:

combine the first output sequence and the second output sequence to obtain a combined output sequence, wherein the combiner logic is configured to add or subtract a respective log-likelihood ratio calculated for each first subcarrier symbol with a respective log-likelihood ratio calculated for the respective second subcarrier symbol to obtain a combined log-likelihood ratio for a respective bit of the bit sequence; and

output the combined output sequence comprising a respective combined log-likelihood ratio for each bit of the bit sequence;

wherein the first subcarrier and the second subcarrier have a phase-based type of modulation and a phase-transform operation has been applied so that the second subcarrier is phase-transformed with respect to the first subcarrier; and

wherein the combiner logic is configured to subtract at least one respective log-likelihood ratio calculated for each second subcarrier symbol from at least one respective log-likelihood ratio calculated for the respective first subcarrier symbol to obtain at least one respective combined log-likelihood ratio.

2. The receiver apparatus of claim 1 , wherein the first subcarrier and the second subcarrier are both modulated using Binary Phase Shift Keying (BPSK) and the second subcarrier is inverted with respect to the first subcarrier, and wherein the combiner logic is configured to subtract the respective log-likelihood ratio calculated for each second subcarrier symbol from the respective log-likelihood ratio calculated for the respective first subcarrier symbol to obtain the combined log-likelihood ratio.

3. The receiver apparatus of claim 1 , wherein the first subcarrier and the second subcarrier are both modulated using Quadrature Phase Shift Keying (QPSK), and wherein the soft-output decoder logic is configured to calculate two respective log-likelihood ratios for each of the first subcarrier symbols and to calculate two respective log-likelihood ratios for each of the second subcarrier symbols, wherein for the respective first subcarrier symbol and second subcarrier symbol corresponding to each symbol period, the combiner logic is configured to:

add a first respective log-likelihood ratio calculated for the first subcarrier symbol to a first respective log-likelihood ratio calculated for the second subcarrier symbol to obtain a first combined log-likelihood ratio; and

subtract a second respective log-likelihood ratio calculated for the second subcarrier symbol from a second respective log-likelihood ratio calculated for the first subcarrier symbol to obtain a second combined log-likelihood ratio.

4. The receiver apparatus of claim 3 , wherein the first respective log-likelihood ratio calculated for the first subcarrier symbol and the first respective log-likelihood ratio calculated for the second subcarrier symbol correspond to one respective bit of the bit sequence, and wherein the second respective log-likelihood ratio calculated for the first subcarrier symbol and the second respective log-likelihood ratio calculated for the second subcarrier symbol correspond to another respective bit of the bit sequence.

5. The receiver apparatus of claim 1 , wherein the soft-output decoder logic comprises Multiple Input Multiple Output (MIMO) decoder logic.

6. A method comprising:

receiving data representative of a received radio signal comprising a first subcarrier comprising first subcarrier symbols and a second subcarrier comprising second subcarrier symbols, wherein the first subcarrier symbols and the second subcarrier symbols both encode a same bit sequence, the bit sequence comprising sets of one or more bits, wherein a respective set of one or more bits is encoded in a respective first subcarrier symbol of the first subcarrier and also in a respective second subcarrier symbol of the second subcarrier, the first subcarrier symbol and second subcarrier symbol occupying a same respective subcarrier symbol period, and wherein the first and second subcarriers have a same type of modulation and different subcarrier frequencies;

calculating one or more respective log-likelihood ratios for each of the first subcarrier symbols and determining a first output sequence comprising the respective log-likelihood ratios calculated for the first subcarrier symbols;

calculating one or more respective log-likelihood ratios for each of the second subcarrier symbols and determining a second output sequence comprising the respective log-likelihood ratios calculated for the second subcarrier symbols; and

combining the first output sequence and the second output sequence to determine a combined output sequence comprising a respective combined log-likelihood ratio for each bit of the bit sequence, wherein combining the first output sequence and the second output sequence comprises adding or subtracting a respective log-likelihood ratio calculated for each first subcarrier symbol with a respective log-likelihood ratio calculated for the respective second subcarrier symbol to obtain a combined log-likelihood ratio for a respective bit of the bit sequence;

wherein:

(A) the first subcarrier and the second subcarrier have a phase-based type of modulation and a phase-transform operation has been applied so that the second subcarrier is phase-transformed with respect to the first subcarrier; and

the method comprises subtracting at least one respective log-likelihood ratio calculated for each second subcarrier symbol from at least one respective log-likelihood ratio calculated for the respective first subcarrier symbol to obtain at least one respective combined log-likelihood ratio;

or

(B) the first subcarrier and the second subcarrier have a phase-based type of modulation and a phase-transform operation has been applied so that the second subcarrier is phase-transformed with respect to the first subcarrier; and

the method comprises:

calculating at least one respective log-likelihood ratio for each of the second subcarrier symbols in dependence upon a transformed channel matrix for the second subcarrier, and

adding each respective log-likelihood ratio calculated for the second subcarrier symbol to a respective log-likelihood ratio calculated for the respective first subcarrier symbol;

or

(C) the first subcarrier and the second subcarrier are both modulated using 16-Quadrature Amplitude Modulation (QAM),

the method comprises:

calculating, for each of the first subcarrier symbols, four respective log-likelihood ratios and generate the first output sequence comprising the respective log-likelihood ratios calculated for the first subcarrier symbols; and

calculating, for each of the second subcarrier symbols, four respective log-likelihood and generate the second output sequence comprising the respective log-likelihood ratios calculated for the second subcarrier symbols, and

the method comprises, for each integer J that is a multiple of four and less the length of the bit sequence:

adding a respective log-likelihood ratio corresponding to a sequence position J in the first output sequence to a respective log-likelihood ratio corresponding to a sequence position J+1 in the second output sequence to obtain a first combined log-likelihood ratio;

adding a respective log-likelihood ratio corresponding to a sequence position J+1 in the first output sequence to a respective log-likelihood ratio corresponding to a sequence position J in the second output sequence to obtain a second combined log-likelihood ratio;

adding a respective log-likelihood ratio corresponding to a sequence position J+2 in the first output sequence to a respective log-likelihood ratio corresponding to a sequence position J+3 in the second output sequence to obtain a third combined log-likelihood ratio; and

adding a respective log-likelihood ratio corresponding to a sequence position J+3 in the first output sequence to a respective log-likelihood ratio corresponding to a sequence position J+2 in the second output sequence to obtain a fourth combined log-likelihood ratio.

7. The method of claim 6 , wherein the radio-frequency signal is an 802.11ax dual carrier modulation (DCM) signal.

8. A non-transitory computer-readable medium storing instructions which, when executed by one or more processors of a receiving apparatus, cause the receiving apparatus to perform the method of claim 6 .

9. A receiver apparatus comprising:

receiving circuitry configured to receive a radio-frequency signal comprising a first subcarrier comprising first subcarrier symbols and a second subcarrier comprising second subcarrier symbols, wherein the first subcarrier symbols and the second subcarrier symbols both encode a same bit sequence, the bit sequence comprising sets of one or more bits, wherein a respective set of one or more bits is encoded in a respective first subcarrier symbol of the first subcarrier and also in a respective second subcarrier symbol of the second subcarrier, the first subcarrier symbol and second subcarrier symbol occupying a same respective symbol period, and wherein the first and second subcarriers have a same type of modulation and different subcarrier frequencies; and

soft-output decoder logic and combiner logic, each comprising respective circuitry or comprising respective software instructions stored in a memory of the receiver apparatus for execution by a processor of the receiver apparatus,

wherein the soft-output decoder logic is configured to:

calculate one or more respective log-likelihood ratios for each of the first subcarrier symbols and generate a first output sequence comprising the respective log-likelihood ratios calculated for the first subcarrier symbols;

calculate one or more respective log-likelihood ratios for each of the second subcarrier symbols and generate a second output sequence comprising the respective log-likelihood ratios calculated for the second subcarrier symbols; and

wherein the combiner logic is configured to:

combine the first output sequence and the second output sequence to obtain a combined output sequence, wherein the combiner logic is configured to add or subtract a respective log-likelihood ratio calculated for each first subcarrier symbol with a respective log-likelihood ratio calculated for the respective second subcarrier symbol to obtain a combined log-likelihood ratio for a respective bit of the bit sequence; and

output the combined output sequence comprising a respective combined log-likelihood ratio for each bit of the bit sequence;

wherein the first subcarrier and the second subcarrier have a phase-based type of modulation and a phase-transform operation has been applied so that the second subcarrier is phase-transformed with respect to the first subcarrier;

wherein the soft-output decoder logic is configured to calculate at least one respective log-likelihood ratio for each of the second subcarrier symbols in dependence upon a transformed channel matrix for the second subcarrier, and

wherein the combiner logic is configured to add each respective log-likelihood ratio calculated for the second subcarrier symbol to a respective log-likelihood ratio calculated for the respective first subcarrier symbol.

10. The receiver apparatus of claim 9 , wherein the first subcarrier and the second subcarrier are both modulated using Binary Phase Shift Keying (BPSK) and the second subcarrier is inverted with respect to the first subcarrier, wherein the soft-output decoder logic is configured to calculate, for each of the second subcarrier symbols, one or more respective log-likelihood ratios in dependence upon an inverted channel matrix for the second subcarrier and generate the second output sequence comprising the respective log-likelihood ratios calculated for the second subcarrier symbols, and wherein the combiner logic is configured to add the respective log-likelihood ratio calculated for each first subcarrier symbol to the respective log-likelihood ratio calculated for the respective second subcarrier symbol to obtain the respective combined log-likelihood ratio.

11. The receiver apparatus of claim 9 , wherein the first subcarrier and the second subcarrier are both modulated using Quadrature Phase Shift Keying (QPSK), and wherein the soft-output decoder logic is configured to:

calculate, for each of the first subcarrier symbols, two respective log-likelihood ratios in dependence upon a channel matrix for the first subcarrier; and

calculate, for each of the second subcarrier symbols, two respective log-likelihood ratios in dependence upon a conjugated channel matrix and a conjugated received symbol for the second subcarrier, and

wherein, for the respective first subcarrier symbol and second subcarrier symbol corresponding to each symbol period, the combiner logic is configured to:

add a first log-likelihood ratio calculated for the first subcarrier symbol to a first log-likelihood ratio calculated for the second subcarrier symbol to obtain a first-bit combined log-likelihood ratio; and

add a second log-likelihood ratio calculated for the second subcarrier symbol to a second log-likelihood ratio calculated for the first subcarrier symbol to obtain a second-bit combined log-likelihood ratio.

12. The receiver apparatus of claim 9 , wherein the soft-output decoder logic comprises Multiple Input Multiple Output (MIMO) decoder logic.

13. A receiver apparatus comprising:

receiving circuitry configured to receive a radio-frequency signal comprising a first subcarrier comprising first subcarrier symbols and a second subcarrier comprising second subcarrier symbols, wherein the first subcarrier symbols and the second subcarrier symbols both encode a same bit sequence, the bit sequence comprising sets of one or more bits, wherein a respective set of one or more bits is encoded in a respective first subcarrier symbol of the first subcarrier and also in a respective second subcarrier symbol of the second subcarrier, the first subcarrier symbol and second subcarrier symbol occupying a same respective symbol period, and wherein the first and second subcarriers have a same type of modulation and different subcarrier frequencies; and

soft-output decoder logic and combiner logic, each comprising respective circuitry or comprising respective software instructions stored in a memory of the receiver apparatus for execution by a processor of the receiver apparatus,

wherein the soft-output decoder logic is configured to:

calculate one or more respective log-likelihood ratios for each of the first subcarrier symbols and generate a first output sequence comprising the respective log-likelihood ratios calculated for the first subcarrier symbols; and

calculate one or more respective log-likelihood ratios for each of the second subcarrier symbols and generate a second output sequence comprising the respective log-likelihood ratios calculated for the second subcarrier symbols; and

wherein the combiner logic is configured to:

combine the first output sequence and the second output sequence to obtain a combined output sequence, wherein the combiner logic is configured to add or subtract a respective log-likelihood ratio calculated for each first subcarrier symbol with a respective log-likelihood ratio calculated for the respective second subcarrier symbol to obtain a combined log-likelihood ratio for a respective bit of the bit sequence; and

output the combined output sequence comprising a respective combined log-likelihood ratio for each bit of the bit sequence;

wherein the first subcarrier and the second subcarrier are both modulated using 16-Quadrature Amplitude Modulation (QAM);

wherein the soft-output decoder logic is configured to:

calculate, for each of the first subcarrier symbols, four respective log-likelihood ratios and generate the first output sequence comprising the respective log-likelihood ratios calculated for the first subcarrier symbols; and

calculate, for each of the second subcarrier symbols, four respective log-likelihood and generate the second output sequence comprising the respective log-likelihood ratios calculated for the second subcarrier symbols, and

wherein the combiner logic is configured, for each integer J that is a multiple of four and less the length of the bit sequence, to:

add a respective log-likelihood ratio corresponding to a sequence position J in the first output sequence to a respective log-likelihood ratio corresponding to a sequence position J+1 in the second output sequence to obtain a first combined log-likelihood ratio;

add a respective log-likelihood ratio corresponding to a sequence position J+1 in the first output sequence to a respective log-likelihood ratio corresponding to a sequence position J in the second output sequence to obtain a second combined log-likelihood ratio;

add a respective log-likelihood ratio corresponding to a sequence position J+2 in the first output sequence to a respective log-likelihood ratio corresponding to a sequence position J+3 in the second output sequence to obtain a third combined log-likelihood ratio; and

add a respective log-likelihood ratio corresponding to a sequence position J+3 in the first output sequence to a respective log-likelihood ratio corresponding to a sequence position J+2 in the second output sequence to obtain a fourth combined log-likelihood ratio.

14. The receiver apparatus of claim 13 , wherein the soft-output decoder logic comprises Multiple Input Multiple Output (MIMO) decoder logic.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 12, 2023
From: VARGHESE, GEORGE
To: NORDIC SEMICONDUCTOR ASA
Reel/Frame 065202/0776 →
Priority Claims (2)
IN 202211052825 · Sep 15, 2022 · national
GB 2217142 · Nov 16, 2022 · national
Continuity (1)
Related Publication 20240097818A1 · Mar 21, 2024
References Cited (7)
US 9294173B2 · Kankipati et al. · 2016 [cited by applicant]
US 20070268988A1 · Hedayat et al. · 2007 [cited by applicant]
US 20160352552A1 · Liu · 2016 [cited by examiner]
US 20210112398A1 · Mishra · 2021 [cited by examiner]
GB 2511370A · 2014 [cited by applicant]
ISO Combined Search and Examination Report under Sections 17 and 18(3) for GB2217142.5, mailed May 16, 2023, 6 pages. [cited by applicant]
Jacob et al., “System-level Performance Comparison of IEEE 802.11p and 802.11bd Draft in Highway Scenarios,” [cited by applicant]