IP Library Patent Application 18372824
Patent Application
App. No. 18/372,824

SECURE TRANSACTION TERMINAL GATEWAY

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Quick Facts
Patent No.
US None
App. No.
18/372,824
Abstract

A secure transaction terminal gateway device is provided. The gateway device includes a single motherboard. The motherboard includes an application processing environment and a security processing environment. Peripheral connections and communications are directly processed and authenticated directly on the security processing environment and indirectly communicated from the secure processing environment to the application processing environment. Communication between the application processing environment and security processing environment is made via an on-motherboard wired secure connection between an application environment port and a security environment port. In an embodiment, the single motherboard is an automated teller machine (ATM) motherboard.

Claims (30)

1 . A system, comprising:

a single motherboard comprising:

an application processing environment;

a secure processing environment; and

a secure wired on-motherboard connection between the application processing environment and the secure processing environment.

2 . The system of claim 1 , wherein secure processing environment includes a secure processor and peripheral ports for peripheral device connections to the secure processing environment.

3 . The system of claim 2 , wherein application processing environment includes an application processor and a secure network port to a secure external network that is external to the single motherboard.

4 . The system of claim 3 , wherein application processing environment includes an application secure port for the secure wired on-motherboard connection and the secure processing environment includes a secure port for the secure wired on-motherboard connection.

5 . The system of claim 1 , wherein the secure processing environment includes a secure processor to execute security applications that authenticate peripheral connections requested of the secure processing environment and that encrypt peripheral communications over the connections.

6 . The system of claim 5 , wherein the application processing environment includes an application processor that executes a media-based transaction application to indirectly communicate with peripheral devices of the connections via the secure wired on-motherboard connection.

7 . The system of claim 1 , wherein the secure processing environment includes a wireless transceiver and a secure processor to execute security applications that authenticate wireless device connections requested of the secure processing environment and that encrypt wireless communications over the wireless device connections.

8 . The system of claim 7 , wherein the application processing environment includes an application processor that executes a media-based transaction application to indirectly communicate with wireless devices of the wireless device connections via the secure wired on-motherboard connection.

9 . The system of claim 1 , wherein single motherboard is an automated teller machine (ATM) motherboard for an ATM device.

10 . The system of claim 1 , wherein the application processing environment is a first independent device, and the secure processing environment is a second independent device, wherein the secure wired on-motherboard connection integrates the first independent device with the second independent device on a single printed circuit board (PCB) as a secure transaction terminal gateway device.

11 . A method, comprising:

controlling application-based operations on an application node;

controlling peripheral-based operations on a security node; and

interfacing the application node and the security node via a secure wired motherboard connection between the application node and the security node.

12 . The method of claim 11 further comprising, processing a media-based transaction on the application node and the security node using the secure wired motherboard connection with peripheral communications directly processed on the security node and indirectly communicated to the application node via secure wired motherboard connection.

13 . The method of claim 12 , wherein processing further includes receiving the peripheral communications over peripheral ports on the security node.

14 . The method of claim 13 , wherein receiving further includes authenticating, by the security node, connections to peripheral devices over the peripheral ports, and encrypting, by the security node, the peripheral communications during the connections.

15 . The method of claim 11 further comprising, processing the method as a secure transaction terminal gateway device for media-based transaction of an automated teller machine (ATM).

16 . The method of claim 11 , wherein controlling the application-based operations further includes interfacing, by the application node, with an external system that is external to the application node and the security node over an external network port on the application node.

17 . The method of claim 16 , wherein controlling the peripheral-based operations further includes authenticating, by the security node, each peripheral device connected to the security node via a corresponding peripheral port of the security node and encrypting, by the security node, communications with a corresponding peripheral device during each authenticated connection.

18 . The method of claim 11 , wherein interfacing further includes encrypting, by the application node and by the security node, communications over the secure wired motherboard connection.

19 . A method, comprising:

providing a first device architecture comprising a first processor, first applications executed by the first processor, and a first secure port;

providing a second device architecture comprising a second processor, second applications executed by the second processor, peripheral ports for peripheral device connections to the second device architecture, and a second secure port;

integrating the first device architecture and the second device architecture on a single printed circuit board (PCB) via a secure wired PCB connection between the first secure port and the second secure port.

20 . The method of claim 19 further includes providing single PCB as an automated teller machine (ATM) motherboard, wherein the peripheral device connections made to peripheral devices via the peripheral ports are authenticated by the second processor and direct communications during the peripheral device connections are encrypted by the second processor.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE PROPERTIES SECTION BY INCLUDING IT WITH TEN PREVIOUSLY OMITTED PROPERTY NUMBERS PREVIOUSLY RECORDED ON REEL 65346 FRAME 367. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 13, 2025
From: NCR ATLEOS CORPORATION; CARDTRONICS USA, LLC
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 072445/0072 →
CHANGE OF NAME Recorded May 20, 2024
From: NCR CORPORATION
To: NCR VOYIX CORPORATION
Reel/Frame 067464/0595 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 20, 2024
From: NCR VOYIX CORPORATION
To: NCR ATLEOS CORPORATION
Reel/Frame 067464/0882 →
CORRECTIVE ASSIGNMENT TO CORRECT THE DOCUMENT DATE AND REMOVE THE OATH/DECLARATION (37 CFR 1.63) PREVIOUSLY RECORDED AT REEL: 065331 FRAME: 0297. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Oct 31, 2023
From: NCR ATLEOS CORPORATION
To: CITIBANK, N.A.
Reel/Frame 065627/0332 →
SECURITY INTEREST Recorded Oct 25, 2023
From: NCR ATLEOS CORPORATION; CARDTRONICS USA, LLC
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 065346/0367 →
SECURITY INTEREST Recorded Oct 24, 2023
From: NCR ATLEOS CORPORATION
To: CITIBANK, N.A.
Reel/Frame 065331/0297 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2023
From: WHYTOCK, ALEXANDER WILLIAM; SLEEMAN, DAVID J.
To: NCR CORPORATION
Reel/Frame 065232/0582 →