Computer device, virtual acceleration device, data transmission method, and storage medium
A virtual acceleration device is deployed for a physical machine. The physical machine and the virtual acceleration device are interconnected through a high-speed serial bus. A serial port device for the physical machine can be virtualized and implemented on the virtual acceleration device. The physical machine can send and receive serial port data through the virtual serial port device. The physical machine only needs to transmit data to the virtual serial port device through the high-speed serial bus, and subsequent transmission actions are completed by the virtual acceleration device. With the advantages of the high-speed serial bus in the transmission speed, the transmission rate of serial port data of the physical machine can be greatly improved, which is beneficial to improving the utilization rate of CPU of the physical machine, and ensuring the stability of service performance of the physical machine.
1 . A computer device, comprising:
a physical machine, and
a virtual acceleration device, wherein:
the virtual acceleration device is connected to the physical machine through a high-speed serial bus, and is a hardware device with software resources;
a virtual serial port device for the physical machine is implemented on the virtual acceleration device, and configured to cooperate with the physical machine to send and receive serial port data; and
the physical machine is configured to identify the virtual serial port device, send and receive the serial port data only through the virtual serial port device without using a built-in serial port device associated with the physical machine, and communicate the serial port data with a target device external to the computer device only through the virtual acceleration device.
2 . The computer device according to claim 1 , wherein multiple registers required by the serial port device are configured on the virtual acceleration device, and the multiple registers are mapped into a configuration space of the virtual acceleration device for implementing virtual serial port devices.
3 . The computer device according to claim 2 , wherein the physical machine is configured to: enumerate devices on the high-speed serial bus, and identify the virtual serial port device according to values of at least some registers in the configuration space when the virtual acceleration device is found.
4 . The computer device according to claim 3 , wherein the physical machine is further configured to:
name the virtual serial port device when the virtual serial port device is identified for a first time, and modify a serial port name in a serial port output parameter in an operating system to be a name of the virtual serial port device.
5 . The computer device according to claim 2 , wherein the virtual acceleration device comprises: a processor, and a memory cache, the memory cache being configured to cache the serial port data sent and received by the physical machine through the virtual serial port device, wherein the processor is configured to read first serial port data written by the physical machine through the virtual serial port device from the memory cache and output the first serial port data, or write second serial port data that the physical machine needs to receive into the memory cache data to allow the virtual serial port device to read and send the second serial port data to the physical machine.
6 . The computer device according to claim 5 , wherein:
the multiple registers comprise at least: a transmission holding register (THR), and a line status register (LSR);
the physical machine is configured to write the first serial port data to the THR through the high-speed serial bus; and
the virtual serial port device is configured to output the first serial port data in the THR to the memory cache, and set a THR status bit in the LSR to 1.
7 . The computer device according to claim 5 , wherein:
the multiple registers comprise at least: a receive buffer register (RBR) and a line status register (LSR);
the virtual serial port device is configured to write the second serial port data that is read from the memory cache into the RBR, and set a data ready status bit of the LSR to 1, and set the data ready status bit of the LSR to 0 after the second serial port data is read; and
the physical machine is configured to read the second serial port data from the RBR through the high-speed serial bus when detecting that the data ready status bit of the LSR is 1.
8 . The computer device according to claim 5 , wherein the virtual acceleration device comprises: a programmable logic device, and a first processing chip, the virtual serial port device being located on the programmable logic device, and the processor and the memory cache being located on the first processing chip.
9 . The computer device according to claim 8 , wherein the programmable logic device is a field programmable logic gate array (FPGA), or a complex programmable logic device (CPLD), and the first processing chip is an application specific integrated circuit (ASIC) chip or a system-on-chip (SOC).
10 . The computer device according to claim 5 , wherein the virtual acceleration device comprises a second processing chip, the virtual serial port device, the processor and the memory cache being all located in the second processing chip.
11 . The computer device according to claim 10 , wherein the second processing chip is an application specific integrated circuit (ASIC) chip or a system-on-chip (SOC).
12 . The device according to claim 1 , wherein the high-speed serial bus is a peripheral component interconnection (PCI) bus or a peripheral component interconnect express (PCIE) bus.
13 . A virtual acceleration device, comprising:
a high-speed serial bus; and
a virtual serial port device implemented for a physical machine, wherein:
the virtual acceleration device is connected to the physical machine through the high-speed serial bus, and
the virtual serial port device is configured to cooperate with the physical machine to send to and receive from a target device external to a computer device including the physical machine and the virtual acceleration device only through the virtual acceleration device, serial port data, when the virtual acceleration device is connected to the physical machine through the high-speed serial bus.
14 . The virtual acceleration device according to claim 13 , further comprising: a processor, the processor being configured to implement the virtual serial port device for the physical machine on the virtual acceleration device, and cooperate with the physical machine to send and receive the serial port data through the virtual serial port device.
15 . The virtual acceleration device according to claim 14 , wherein: when the processor implements the virtual serial port device on the virtual acceleration device, the device is configured to:
configure multiple registers required by the serial port device, and map the multiple registers into a configuration space of the virtual acceleration device for implementing the virtual serial port device.
16 . The virtual acceleration device according to claim 15 , further comprising: a memory cache configured to cache the serial port data sent and received by the physical machine through the virtual serial port device, wherein:
when the processor cooperates with the physical machine to send and receive the serial port data through the virtual serial port device, the device is configured to: read first serial port data written by the physical machine through the virtual serial port device from the memory cache, and output the first serial port data, or write second serial port data to be received by the physical machine into the memory cache, to allow the virtual serial port device to read and send the second serial port data to the physical machine.
17 . The virtual acceleration device according to claim 16 , wherein:
the multiple registers comprise at least: a transmission holding register (THR), and a line status register (LSR); and
the virtual serial port device is configured to output the first serial port data in the THR to the memory cache after the physical machine writes the first serial port data into the THR through the high-speed serial bus, and set a THR status bit of LSR to 1.
18 . The virtual acceleration device according to claim 16 , wherein:
the multiple registers comprise at least: a receive buffer register (RBR) and a line status register (LSR); and
the virtual serial port device is configured to write the second serial port data that is read from the memory cache into the RBR, and set a data ready status bit of the LSR to 1, to allow the physical machine to read the second serial port data from the RBR through the high-speed serial bus, and set the data ready status bit of the LSR to 0 after the second serial port data is read.
19 . A physical machine comprising:
a memory; and
a processor, wherein:
the memory is configured to store a computer program;
the processor, which is coupled with the memory, is configured to execute the computer program to: identify a virtual serial port device, and send and receive serial port data from a target device external to a computer device including the physical machine and a virtual acceleration device only through the virtual serial port device, wherein the virtual serial port device is implemented on the virtual acceleration device connected to the physical machine through a high-speed serial bus.
20 . The physical machine according to claim 19 , wherein: when the processor identifies the virtual serial port device, the device is configured to:
enumerate devices on the high-speed serial bus, and identify the virtual serial port device according to values of at least some registers in a configuration space of the virtual acceleration device when the virtual acceleration device is found.