IP Library Granted Patent US 12,625,639
Granted Patent B2
US 12,625,639 · App. 18/380,945 · Granted May 12, 2026

Storage device and operating method of storage device

Inventors: Youngmin Lee (Suwon-si, KR); Seongheum Baik (Suwon-si, KR); Myungsub Shin (Suwon-si, KR); Seongyong Jang (Suwon-si, KR); Gyuseok Choe (Suwon-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
G06F3/0652G06F3/0607G06F3/064G06F3/0679
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Quick Facts
Patent No.
US 12,625,639
App. No.
18/380,945
Granted
May 12, 2026
Kind
B2
Abstract

Disclosed is a storage device which includes a nonvolatile memory device that includes a plurality of erase units each including a plurality of memory cells, and a memory controller. Based on an open zone request received from an external host device, the memory controller allocates a zone to at least one erase unit among the plurality of erase units and permits only a sequential write with respect to the zone. The memory controller generates a map table mapping sequential logical addresses of data written in the zone to sequential physical addresses. Based on a partial invalidation request received from the external host device, the memory controller manages data corresponding to the partial invalidation request from among the data written in the zone as invalid data while maintaining the map table.

Claims (48)

1 . A storage device comprising:

a nonvolatile memory device comprising a plurality of erase units each comprising a plurality of memory cells; and

a memory controller,

wherein, based on an open zone request received from an external host device, the memory controller is configured to allocate a zone to at least one erase unit among the plurality of erase units and to permit only a sequential write with respect to the zone,

wherein the memory controller is further configured to generate a map table, and the map table maps sequential logical addresses of first data written in the zone to sequential physical addresses,

wherein, based on a partial invalidation request received from the external host device, the memory controller is further configured to manage second data, from among the first data that corresponds to the partial invalidation request, as invalid data while maintaining the map table with the sequential logical addresses and the sequential physical addresses of the first data written in the zone without updating the map table until a garbage collection operation, and

wherein, during the garbage collection operation, the memory controller is further configured to sequentially copy the first data, except for the second data corresponding to the partial invalidation request, to a second zone, and generate a second map table mapping sequential logical addresses of the copied first data in the second zone.

2 . The storage device of claim 1 , wherein the memory controller is further configured to:

increase a valid page count of the zone based on first page data being written to the zone; and

decrease the valid page count of the zone based on the first page data being invalidated.

3 . The storage device of claim 2 , wherein, based on the valid page count being different from a page number pointed out by a write pointer, the memory controller is further configured to determine that at least one of pages of the zone, at which the first data are written, stores invalid page data.

4 . The storage device of claim 1 , wherein each page of the zone corresponds to two or more logical addresses, and

wherein the memory controller is further configured to:

set a relevant bit of a bitmap of the zone to a valid value based on third data being written at to the zone, wherein the third data corresponds to a first logical address; and

set the relevant bit of the bitmap of the zone to an invalid value based on the third data being invalidated.

5 . The storage device of claim 1 , wherein the partial invalidation request comprises two or more logical addresses.

6 . The storage device of claim 1 , wherein the partial invalidation request comprises two or more logical address ranges, and

wherein each of the two or more logical address ranges comprises a start logical address and a length.

7 . The storage device of claim 1 , wherein the memory controller is further configured to transmit invalid pattern data to the external host device, based on a read request for the invalid data received from the external host device.

8 . The storage device of claim 7 , wherein the memory controller is further configured to transmit the invalid pattern data to the external host device without a read operation of the nonvolatile memory device.

9 . The storage device of claim 7 , wherein the memory controller is further configured to transmit a response indicating the invalid pattern data after transmitting the invalid pattern data to the external host device.

10 . The storage device of claim 1 , wherein, while the memory controller is further configured to manage the second data corresponding to the partial invalidation request as the invalid data, the nonvolatile memory device is configured to retain original valid data corresponding to the partial invalidation request.

11 . The storage device of claim 10 , wherein the memory controller is further configured to delete the map table in response to that a reset request of the zone is received from the external host device.

12 . The storage device of claim 11 , wherein an access to the invalid data is prohibited based on that the map table is deleted.

13 . A storage device comprising:

a nonvolatile memory device comprising a plurality of erase units each comprising a plurality of memory cells; and

a memory controller,

wherein, based on an open zone request received from an external host device, the memory controller is configured to allocate a zone to at least one erase unit among the plurality of erase units and to permit only a sequential write with respect to the zone,

wherein the memory controller is further configured to generate a map table, and the map table maps sequential logical addresses of first data written in the zone to sequential physical addresses,

wherein, based on a partial invalidation request received from the external host device, the memory controller is further configured to perform an overwrite operation with respect to second data, from among the first data that corresponds to the partial invalidation request, while maintaining the map table with the sequential logical addresses and the sequential physical addresses of the first data written in the zone without updating the map table until a garbage collection operation, and

wherein, during the garbage collection operation, the memory controller is further configured to sequentially copy the first data, except for the second data corresponding to the partial invalidation request, to a second zone, and generate a second map table mapping sequential logical addresses of the copied first data in the second zone.

14 . The storage device of claim 13 , wherein, when data are written to the zone, the nonvolatile memory device is further configured to program memory cells of each page of the zone to a state among an erase state and a plurality of program states, and

wherein, in the overwrite operation, the nonvolatile memory device is further configured to increase threshold voltages of the memory cells having the erase state and at least one program state of the plurality of program states so as to overlap some of remaining program states other than the at least one program state of the plurality of program states.

15 . The storage device of claim 13 , wherein, based on the first data being written to the zone, the nonvolatile memory device is further configured to apply program voltages, whose levels belong to a range from a program start voltage to a program end voltage, to memory cells of a page, and

wherein, in the overwrite operation, the nonvolatile memory device is further configured to apply at least one overwrite voltage to second memory cells of the page, wherein the second memory cells correspond to the partial invalidation request.

16 . The storage device of claim 15 , wherein the at least one overwrite voltage has a level between the program start voltage and the program end voltage.

17 . The storage device of claim 16 , wherein the at least one overwrite voltage comprises at least two overwrite voltages with different levels.

18 . The storage device of claim 13 , wherein, based on the partial invalidation request received from the external host device, the memory controller is further configured to manage the second data corresponding to the partial invalidation request from among the first data written in the zone as invalid while maintaining the map table.

19 . The storage device of claim 18 , wherein the memory controller is further configured to transmit invalid pattern data to the external host device, based on a read request for the second data received from the external host device.

20 . An operating method of a storage device comprising a nonvolatile memory device and a memory controller, the operating method comprising:

generating a map table that maps sequential logical addresses of first data written in a zone to sequential physical addresses;

setting a partial invalidation request to one of a first mode, a second mode, and a third mode depending on a request of an external host device;

in the first mode, managing, at the memory controller, second data corresponding to the partial invalidation request as being invalid based on the partial invalidation request received from the external host device;

in the second mode, based on the partial invalidation request received from the external host device, causing, by the memory controller, the nonvolatile memory device to perform an overwrite operation with respect to the second data, from among the first data that corresponds to the partial invalidation request, and managing the second data as being invalid;

in the third mode, based on the partial invalidation request received from the external host device:

sequentially copying, by the memory controller to a second memory block during a garbage collection operation, the first data except for the second data corresponding to the partial invalidation request and generating a second map table mapping sequential logical addresses of the copied first data in the second memory block, the second data being among third data of a memory block corresponding to the partial invalidation request, and

erasing the memory block corresponding to the partial invalidation request; and

maintaining the map table with the sequential logical addresses and the sequential physical addresses of the first data written in the zone without updating the map table until the garbage collection operation.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 17, 2023
From: LEE, YOUNGMIN; BAIK, SEONGHEUM; SHIN, MYUNGSUB; JANG, SEONGYONG; CHOE, GYUSEOK
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 065254/0095 →
Priority Claims (1)
KR 10-2023-0057247 · May 2, 2023 · national
Continuity (1)
Related Publication 20240370196A1 · Nov 7, 2024
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