Mismatch error calibration method and apparatus of a time interleaving digital-to-analog converter
A mismatch error calibration method and apparatus of a time interleaved digital-to-analog converter. The method includes: sampling an output signal of a time interleaved digital-to-analog converter to obtain a measurement signal; preprocessing the measurement signal to obtain a preprocessed measurement signal; and estimating a coefficient of a digital impairment equalizer according to an input signal of the digital impairment equalizer, an output signal of the digital impairment equalizer, and the preprocessed measurement signal. By preprocessing a non-ideal feedback channel, interferences caused by non-ideality of the feedback channel is eliminated, so as to achieve better mismatch error calibration performance of a TI-DAC.
1. A mismatch error calibration apparatus of a time interleaved digital-to-analog converter, comprising:
a memory; and
a processor coupled to the memory to control execution of a process to:
sample an output signal of the time interleaved digital-to-analog converter to obtain a measurement signal:
preprocess the measurement signal to obtain a preprocessed measurement signal:
estimate a coefficient of a digital impairment equalizer according to an input signal of the digital impairment equalizer, an output signal of the digital impairment equalizer, and the preprocessed measurement signal.
2. The mismatch error calibration apparatus according to claim 1 , wherein,
the measurement signal includes impairment and interference introduced by a non-ideal measurement feedback channel:
the non-ideal measurement feedback channel includes a physical connection device connected to the time interleaved digital-to-analog converter, and a receiving equipment.
3. The mismatch error calibration apparatus according to claim 1 , wherein,
the processor takes an input signal of the time interleaved digital-to-analog converter as a reference, and filters the measurement signal by using a finite impulse response filter, to obtain the preprocessed measurement signal.
4. The mismatch error calibration apparatus according to claim 1 , wherein the execution of the process by the processor further comprises:
performing serial-to-parallel conversion on a signal to be transmitted to obtain parallel digital signals of M paths as input signals of the digital impairment equalizer, M being a number of sub digital-to-analog converters contained in the time interleaved digital-to-analog converter:
performing pre-equalization processing on the parallel digital signals of M paths according to the coefficient of the digital impairment equalizer, to obtain equalized signals as output signals of the digital impairment equalizer; and
performing parallel-to-serial conversion on the output signals of the digital impairment equalizer to obtain a serial digital signal as an input signal of the time interleaved digital-to-analog converter.
5. The mismatch error calibration apparatus according to claim 4 , wherein,
the digital impairment equalizer is composed of a M×M multi-input multi-output finite impulse response filter and a coefficient vector for compensating direct current bias of a sub digital-to-analog converter of each path.
6. The mismatch error calibration apparatus according to claim 5 , wherein,
the digital impairment equalizer is represented as:
H
=
[
H
1
;
H
2
;
…
;
H
M
]
T
=
[
h
11
⋯
0
⋮
⋱
⋮
0
⋯
h
MM
]
+
[
h
1
b
⋮
h
M
b
]
the output signals of the digital impairment equalizer are represented as:
S
=
[
s
1
[
n
]
⋮
s
M
[
n
]
]
=
[
h
11
*
x
1
[
n
]
⋮
h
MM
*
x
M
[
n
]
]
+
[
h
1
b
⋮
h
M
b
]
wherein, H m is a m-th path digital impairment equalizer: S m [n] is an output signal of the m-th path digital impairment equalizer: h mm is a finite impulse response filter corresponding to the m-th path digital impairment equalizer; h m b is a coefficient for compensating direct current bias, of the m-th path digital impairment equalizer: x m [n] is input signals of the digital impairment equalizer; m=1, 2, 3, . . . , M, M is the number of sub digital-to-analog converters contained in the time interleaved digital-to-analog converter.
7. The mismatch error calibration apparatus according to claim 1 , wherein the coefficient of the digital impairment equalizer is estimated by:
processing output signals of the digital impairment equalizer according to a current coefficient of an estimator, to obtain an estimated value of the output signal of the time interleaved digital-to-analog converter; and
calculating a coefficient of the digital impairment equalizer according to input signals of the digital impairment equalizer, the estimated value of the output signal of the time interleaved digital-to-analog converter, and the current coefficient of the estimator.
8. The mismatch error calibration apparatus according to claim 7 , wherein,
the estimator is composed of a M×M multi-input multi-output finite impulse response filter and a coefficient vector for characterizing direct current bias of a sub digital-to-analog converter of each path.
9. The mismatch error calibration apparatus according to claim 8 , wherein,
the estimator is represented as:
G
ˆ
=
[
G
ˆ
1
;
G
ˆ
2
;
…
;
G
ˆ
M
]
T
=
[
g
^
11
⋯
0
⋮
⋱
⋮
0
⋯
g
^
MM
]
+
[
g
^
1
b
⋮
g
^
M
b
]
the output signals of the estimator are represented as:
Y
ˆ
=
[
y
^
1
[
n
]
⋮
y
^
M
[
n
]
]
=
[
g
^
11
*
s
1
[
n
]
⋮
g
^
MM
*
s
M
[
n
]
]
+
[
g
^
1
b
⋮
g
^
M
b
]
wherein, Ĝ m is a m-th path estimator: ŷ m [n] is an output signal of the m-th path estimator: ĝ mm is a finite impulse response filter corresponding to the m-th path estimator: ĝ m b is a coefficient for characterizing direct current bias, of the m-th path estimator: s m [n] is an input signal of the m-th path estimator; m=1, 2, 3, . . . , M, M is a number of sub digital-to-analog converters contained in the time interleaved digital-to-analog converter.
10. The mismatch error calibration apparatus according to claim 7 , wherein the coefficient of the digital impairment equalizer is estimated by:
performing serial-to-parallel conversion on the preprocessed measurement signal to obtain parallel digital signals of M paths, M being a number of sub digital-to-analog converters contained in the time interleaved digital-to-analog converter; and
calculating the coefficient of the estimator by using the parallel digital signals of M paths, the output signals of the digital impairment equalizer and the estimated value of the output signal of the time interleaved digital-to-analog converter.