NORMALLY-ON GAN HEMT INTEGRATION ON MONOLITHIC P-GAN INTEGRATED CIRCUITS
Methods, systems, and apparatuses for normally-on GaN high electron mobility transistors (HEMT) integration on monolithic p-GaN integrated circuits (ICs) platforms are provided. In particular, the integrated circuit platforms may include both enhancement mode and depletion mode HEMT power devices in monolithically integrated p-GaN power ICs. Exemplary methods may include treating at least one of a plurality of p-GaN gates with an in-situ plasma treatment to deactivate Mg in the p-GaN gate treated and deplete this p-Gan gate of Mg. The depleted p-GaN gate may be the gate for the normally on HEMT in the IC. At least one of the p-GaN gates not exposed to the in-situ plasma pretreatment may be the gate of the normally off HEMT in the IC.
1 . A method for manufacturing an integrated circuit platform comprising:
providing a wafer comprising a AlGaN layer with a first surface and a p-GaN layer on the first of the AlGaN layer;
etching the p-GaN layer to form at least a first p-GaN gate and a second p-GaN gate;
depositing a first silicon based dielectric layer over the first p-GaN gate, the second p-GaN gate, and the AlGaN layer;
etching the first silicon based dielectric layer to expose the second p-GaN gate and a first portion of the AlGaN layer;
treating the second p-GaN gate and the first portion of the AlGaN layer with an in-situ plasma treatment, wherein the in-situ plasma treatment deactivates magnesium in the second p-GaN gate to form a depleted p-GaN gate; and
forming at least a first normally-off HEMT and at least a first normally-on HEMT, wherein the gate of the first normally-off HEMT is the first p-GaN gate, and wherein a gate of the first normally-on HEMT is the depleted p-GaN gate.
2 . The method of claim 1 , wherein forming the first normally-off HEMT comprises forming a plurality of alumina layers; and
wherein forming the first normally-on HEMT comprises a single alumina layer.
3 . The method of claim 1 , wherein the first silicon based dielectric layer has a thickness of 70 nm.
4 . The method of claim 1 , wherein the in-situ plasma treatment is comprises diffusing hydrogen into the second p-GaN gate and the AlGaN layer.
5 . The method of claim 1 , wherein the in-situ plasma treatment deactivates magnesium in the first portion of the AlGaN layer.
6 . The method of claim 1 , wherein forming the first normally-off HEMT further comprises depositing metallization layers associated with a first normally-off HEMT gate, a first normally-off HEMT source, and a first normally-off HEMT drain; and
wherein forming the first normally-on HEMT further comprises depositing metallization layers associated with a first normally-on HEMT gate, a first normally-on HEMT source, and a first normally-on HEMT drain.
7 . The method of claim 6 , wherein forming the first normally-off HEMT further comprises depositing at least a first metal shielding layer; and
wherein forming the first normally-on HEMT further comprises depositing at least a second metal shielding layer.
8 . The method of claim 1 , wherein the depleted p-GaN gate of the first normally-on HEMT has a flat capacitance trend as voltage increases.
9 . The method of claim 1 , wherein the p-GaN gate of the first normally-off HEMT has a Schottky capacitance trend as voltage increases.
10 . The method of claim 1 , wherein providing the wafer further comprises providing a TiN layer covering the p-GaN layer; and
wherein the first p-GaN gate of the first normally-off HEMT is covered by a first portion of the TiN layer; and wherein the depleted p-GaN gate of the first normally-on HEMT is covered by a second TiN layer.
11 . An integrated circuit platform comprising:
a normally-off HEMT and a normally-on HEMT;
wherein the normally-off HEMT is comprised of a p-doped GaN gate on an AlGaN layer; and
wherein the normally-on HEMT is comprised of a depleted p-GaN gate deactivated with an in-situ plasma treatment on the AlGaN layer.
12 . The integrated circuit platform of claim 11 , wherein the normally-off HEMT further comprises a plurality of alumina layers; and
wherein the normally-on HEMT further comprises a single alumina layer.
13 . The integrated circuit platform of claim 11 further comprising a first silicon based dielectric layer, wherein the first silicon based dielectric layer has a thickness of 70 nm.
14 . The integrated circuit platform of claim 11 , wherein the depleted p-GaN gate comprises Mg—H formed from diffusing hydrogen into the depleted p-GaN gate.
15 . The integrated circuit platform of claim 11 further comprising a first portion of the AlGaN layer, wherein the first portion of the AlGaN layer comprises deactivated magnesium from exposure to the in-situ plasma treatment.
16 . The integrated circuit platform of claim 11 , wherein the normally-off HEMT further comprises metallization layers associated with a normally-off HEMT gate, a normally-off HEMT source, and a normally-off HEMT drain; and
wherein the normally-on HEMT further comprises metallization layers associated with a normally-on HEMT gate, a normally-on HEMT source, and a normally-on HEMT drain.
17 . The integrated circuit platform of claim 16 , wherein the normally-off HEMT further comprises at least a first metal shielding layer; and
wherein the normally-on HEMT further comprises at least a second metal shielding layer.
18 . The integrated circuit platform of claim 11 , wherein the depleted p-GaN gate of the normally-on HEMT has a flat capacitance trend as voltage increases.
19 . The integrated circuit platform of claim 11 , wherein the p-doped GaN gate of the normally-off HEMT has a Schottky capacitance trend as voltage increases.
20 . The integrated circuit platform of claim 11 , wherein the p-doped GaN gate is covered by a first TiN layer; and wherein the depleted p-GaN gate is covered by a second TiN layer.