Lifetime mixed level non-volatile memory system

1. A system for storing data comprising:

an MLC non-volatile memory space including at least one MLC non-volatile memory element;

an SLC non-volatile memory module space including at least one SLC non- volatile memory element; and

a controller coupled to the at least one MLC non-volatile memory element and the at least one SLC non-volatile memory element wherein the controller is adapted to:

a) maintain an address map of the MLC and SLC non-volatile memory spaces, the address map comprising a list of logical address ranges accessible by a computer system, the list of logical address ranges having a minimum quanta of addresses, wherein each entry in the list of logical address ranges maps to a similar range of physical addresses within either the at least one SLC non-volatile memory element or within the at least one MLC non-volatile memory element;

b) determine if a range of addresses listed by an entry and mapped to a similar range of physical addresses within the at least one MLC non-volatile memory element, fails a data integrity test performed at the controller based upon received data retained at the controller and which received data is stored in the at least one MLC non-volatile memory element as stored data, and, in an event of such a failure, the controller remaps the entry to a next available equivalent range of physical addresses within the at least one SLC non-volatile memory element and, the stored data is transferred from the at least one MLC non-volatile memory element to the at least one SLC non-volatile memory element.

2. The system of claim 1 , wherein the minimum quanta of addresses is equal to one block.

3. The system of claim 1 , wherein the minimum quanta of addresses is equal to one page.

4. The system of claim 1 , wherein the at least one MLC non-volatile memory element is NAND flash memory.

5. The system of claim 1 , wherein the at least one SLC non-volatile memory element is NAND flash memory.

6. The system of claim 1 , wherein the at least one MLC non-volatile memory element is resistive random-access memory (RRAM).

7. The system of claim 1 , wherein the at least one SLC non-volatile memory element is resistive random-access memory (RRAM).

8. The system of claim 1 , wherein the at least one MLC non-volatile memory element is phase change memory (PCM).

9. The system of claim 1 , wherein the at least one SLC non-volatile memory element is phase change memory (PCM).

10. The system of claim 1 , wherein the at least one SLC non-volatile memory element is magnetic random-access memory (MA-GRAM).

11. The system of claim 1 , wherein the controller causes a transfer of content on a periodic basis.

12. The system of claim 1 , wherein the at least one MLC non-volatile memory element and the at least one SLC non-volatile memory element comprise a block with physical addresses.

13. The system of claim 1 , wherein the at least one MLC non-volatile memory element and the at least one SLC non-volatile memory element comprise a page with physical addresses.

14. The system of claim 1 , wherein the transfer of the stored data from the at least one MLC non-volatile memory element to the at least one SLC non-volatile memory element is temporary.

15. The system of claim 1 , wherein the transfer of the stored data from the at least one MLC non-volatile memory element to the at least one SLC non-volatile memory element is temporary until an MLC non-volatile memory element is available.

16. The system of claim 1 , wherein operations of the controller enhance a lifetime of the at least one MLC non-volatile memory element and the at least one SLC non-volatile memory element.

17. The system of claim 1 , wherein the controller determines during a write operation if the range of addresses listed by the entry and mapped to the similar range of physical addresses within the at least one MLC non-volatile memory element, fails the data integrity test.

18. A method for storing data comprising:

providing an MLC non-volatile memory space including at least one MLC non-volatile memory element;

providing an SLC non-volatile memory space including at least one SLC non-volatile memory element; and

maintaining, using a controller coupled to the at least one MLC non-volatile memory element and the at least one SLC non-volatile memory element, an address map of the MLC and SLC non-volatile memory spaces, the address map comprising a list of logical address ranges accessible by a computer system, the list of logical address ranges having a minimum quanta of addresses, wherein each entry in the list of logical address ranges maps to a similar range of physical addresses within either the at least one SLC non-volatile memory element or within the at least one MLC non-volatile memory element;

determining, using the controller, if a range of addresses listed by an entry and mapped to a similar range of physical addresses within the at least one MLC non-volatile memory element, fails a data integrity test performed at the controller based upon received data retained at the controller and which received data is stored in the at least one MLC non-volatile memory element as stored data;

in an event of such a failure,

remapping, using the controller, the entry to a next available equivalent range of physical addresses within the at least one SLC non-volatile memory element; and

transferring the stored data from the at least one MLC non-volatile memory element to the at least one SLC non-volatile memory element using the controller.