IP Library Granted Patent US 12,314,128
Granted Patent B2
US 12,314,128 · App. 18/397,450 · Granted May 27, 2025

Channel modulation for a memory device

Inventors: Martin Brox (Munich, DE); Peter Mayer (Neubiberg, DE); Wolfgang Anton Spirkl (Germering, DE); Thomas Hein (Munich, DE); Michael Dieter Richter (Ottobrunn, DE); Timothy M. Hollis (Meridian, ID); Roy Greeff (Boise, ID)
G06F11/1004G06F11/16G06F12/02
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Quick Facts
Patent No.
US 12,314,128
App. No.
18/397,450
Granted
May 27, 2025
Kind
B2
Abstract

Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.

Claims (44)

1. A method at a memory device, comprising:

identifying, from a mode register of the memory device, a first quantity of voltage levels associated with a first modulation scheme;

configuring the memory device, for communications over a channel coupled with the memory device, with the first modulation scheme using the first quantity of voltage levels based at least in part on identifying the first quantity of voltage levels;

communicating signaling over the channel coupled with the memory device based at least in part on the configuring, the signaling modulated with the first modulation scheme using the first quantity of voltage levels; and

transmitting error detection signaling over an error detection channel coupled with the memory device, the error detection signaling modulated with a second modulation scheme using a second quantity of voltage levels different than the first quantity of voltage levels.

2. The method of claim 1 , wherein configuring the memory device with the first modulation scheme comprises:

configuring the memory device, based at least in part on identifying the first quantity of voltage levels, with the first modulation scheme using two voltage levels, wherein the second modulation scheme uses three or more voltage levels.

3. The method of claim 1 , wherein configuring the memory device with the first modulation scheme comprises:

configuring the memory device, based at least in part on identifying the first quantity of voltage levels, with the first modulation scheme associated with a first range of voltages, wherein the second modulation scheme is associated with a second range of voltages that is different than the first range of voltages.

4. The method of claim 1 , wherein the channel is a data channel coupled with the memory device.

5. The method of claim 4 , wherein communicating the signaling over the channel comprises:

transmitting, over the data channel, data signaling that is modulated with the first modulation scheme using the first quantity of voltage levels.

6. The method of claim 4 , wherein communicating the signaling over the channel comprises:

receiving, over the data channel, data signaling that is modulated with the first modulation scheme using the first quantity of voltage levels.

7. A memory device, comprising:

a receiver;

a transmitter; and

one or more processors configured to cause the memory device to:

identify, from a mode register of the memory device, a first quantity of voltage levels associated with a first modulation scheme;

configure the memory device, for communications via the receiver, the transmitter, or both, with the first modulation scheme using the first quantity of voltage levels based at least in part on identifying the first quantity of voltage levels;

communicate signaling via the receiver, the transmitter, or both based at least in part on the configuring, the signaling modulated with the first modulation scheme using the first quantity of voltage levels; and

transmit error detection signaling via the transmitter, the error detection signaling modulated with a second modulation scheme using a second quantity of voltage levels different than the first quantity of voltage levels.

8. The memory device of claim 7 , wherein, to configure the memory device with the first modulation scheme, the one or more processors are configured to cause the memory device to:

configure the memory device, based at least in part on identifying the first quantity of voltage levels, with the first modulation scheme using two voltage levels, wherein the second modulation scheme uses three or more voltage levels.

9. The memory device of claim 7 , wherein the receiver, the transmitter, or both are configured for coupling with a data channel.

10. A method at a memory device, comprising:

determining, from a mode register of the memory device, a first quantity of voltage levels of a first modulation scheme for a data channel coupled with the memory device, the first quantity of voltage levels being two voltage levels or three or more voltage levels;

configuring the memory device, for communications over the data channel coupled with the memory device, with the first modulation scheme using the determined first quantity of voltage levels;

communicating signaling over the data channel coupled with the memory device based at least in part on the configuring, the signaling modulated with the first modulation scheme using the determined first quantity of voltage levels; and

transmitting error detection signaling over an error detection channel coupled with the memory device, the error detection signaling modulated with a second modulation scheme using a second quantity of voltage levels different than the first quantity of voltage levels.

11. A method at a host device, comprising:

identifying, from a mode register, a first quantity of voltage levels associated with a first modulation scheme;

configuring the host device to use the first modulation scheme for communications over a channel coupled with the host device based at least in part on identifying the first quantity of voltage levels;

communicating signaling over the channel coupled with the host device based at least in part on the configuring, the signaling modulated with the first modulation scheme using the first quantity of voltage levels; and

transmitting error detection signaling over an error detection channel coupled with the host device, the error detection signaling modulated with a second modulation scheme using a second quantity of voltage levels different than the first quantity of voltage levels.

12. The method of claim 11 , wherein configuring the host device with the first modulation scheme comprises:

configuring the host device, based at least in part on identifying the first quantity of voltage levels, with the first modulation scheme using two voltage levels, wherein the second modulation scheme uses three or more voltage levels.

13. The method of claim 11 , wherein configuring the host device with the first modulation scheme comprises:

configuring the host device, based at least in part on identifying the first quantity of voltage levels, with the first modulation scheme associated with a first range of voltages, wherein the second modulation scheme is associated with a second range of voltages that is different than the first range of voltages.

14. The method of claim 11 , wherein the channel is a data channel coupled with the host device.

15. The method of claim 14 , wherein communicating over the channel comprises:

transmitting, over the data channel, first signaling that is modulated with the first modulation scheme using the first quantity of voltage levels.

16. The method of claim 14 , wherein communicating over the channel comprises:

receiving, over the data channel, second signaling that is modulated with the first modulation scheme using the first quantity of voltage levels.

Continuity (4)
Continuation 17857700 · Jul 5, 2022
Continuation 16744025 · Jan 15, 2020
Provisional Application 62793585 · Jan 17, 2019
Related Publication 20240126644A1 · Apr 18, 2024
References Cited (21)
US 9734898B2 · Seol et al. · 2017 [cited by applicant]
US 9870834B2 · Li et al. · 2018 [cited by applicant]
US 10128842B1 · Lin · 2018 [cited by applicant]
US 11392451B2 · Parry · 2022 [cited by examiner]
US 20060140287A1 · Alon et al. · 2006 [cited by applicant]
US 20090080266A1 · Zumkehr · 2009 [cited by examiner]
US 20100244905A1 · Kim · 2010 [cited by examiner]
US 20100297949A1 · Nakajima · 2010 [cited by applicant]
US 20130023298A1 · Chen et al. · 2013 [cited by applicant]
US 20140082455A1 · Yosoku et al. · 2014 [cited by applicant]
US 20140362786A1 · Kelman et al. · 2014 [cited by applicant]
US 20150085914A1 · Kizer et al. · 2015 [cited by applicant]
US 20150193321A1 · Ngo et al. · 2015 [cited by applicant]
US 20150280693A1 · Jung · 2015 [cited by examiner]
US 20160004597A1 · Tsern et al. · 2016 [cited by applicant]
US 20190034328A1 · Sato · 2019 [cited by examiner]
US 20190103143A1 · Hasbun et al. · 2019 [cited by applicant]
US 20190278359A1 · Kim · 2019 [cited by examiner]
European Patent Office, “Supplementary European search report and Search Opinion”, issued in connection with European Patent Application No. 20740951 dated Mar. 28, 2022 (7 pages). [cited by applicant]
International Search Report and Written Opinion received for PCT Patent Application No. PCT/US20/13818, mailed on May 13, 2020, 9 pages. [cited by applicant]
Korean patent office, “KR Office Action,” issued in connection with Korean Patent Application No. 10-2021-7024998 dated Nov. 27, 2023 (17 pages) (6 pages of English Translation and 11 pages of Original Document). [cited by applicant]