Semiconductor components having conductive vias with aligned back side conductors
A semiconductor component includes a semiconductor substrate, conductive vias in the substrate having terminal portions, a polymer layer on the substrate and back side conductors formed by the terminal portions of the conductive vias embedded in the polymer layer. A stacked semiconductor component includes a plurality of components having aligned conductive vias in electrical communication with one another.
1. A method for manufacturing a semiconductor device, the method comprising:
forming a plurality of circuit side conductors on a circuit side of a semiconductor substrate, each of the plurality of circuit side conductors is electrically coupled to at least one of a plurality of conductive vias in the semiconductor substrate, wherein the plurality of conductive vias each extend from the circuit side to a back side opposite the circuit side;
forming an outer dielectric layer on the circuit side having openings each aligned with an individual one of the plurality of conductive vias;
removing portions of the semiconductor substrate from the back side to expose a terminal portion of each of the plurality of conductive vias at the back side such that a terminal surface on the terminal portion of each of the plurality of conductive vias is at least a first distance from the back side;
depositing a polymer layer on the back side such that an outer surface of the polymer layer is a second distance from the back side, wherein the second distance is equal to or greater than the first distance such that the polymer layer encapsulates the terminal portion of each of the plurality of conductive vias;
planarizing the polymer layer and the terminal portion of each of the plurality of conductive vias to form a plurality of conductive contacts spaced apart from the back side, wherein each of the plurality of conductive contacts is self-aligned with a corresponding one of the plurality of conductive vias; and
forming a plurality of terminal contacts, each of the plurality of terminal contacts electrically coupled to one of the plurality of conductive contacts.
2. The method of claim 1 , further comprising forming a dielectric layer on the circuit side of the semiconductor substrate before forming the plurality of circuit side conductors, wherein the dielectric layer includes a plurality of openings each individually corresponding to one of the plurality of conductive vias.
3. The method of claim 1 wherein each of the plurality of circuit side conductors is in electrical contact with a sidewall of the at least one of the plurality of conductive vias.
4. The method of claim 1 wherein forming the plurality of terminal contacts comprises forming an under bump metallization layer on each of the plurality of conductive contacts.
5. The method of claim 1 wherein forming the plurality of terminal contacts comprises:
forming a plurality of back side redistribution conductors, each of the plurality of back side redistribution conductors coupled to an individual one of the plurality of conductive contacts; and
forming each of the plurality of terminal contacts on a corresponding one of the plurality of back side redistribution conductors.
6. The method of claim 1 wherein, after planarizing the polymer layer and the terminal portion of each of the plurality of conductive vias, the terminal surface on the terminal portion of each of the plurality of conductive vias is a third distance from the back side that is less than the first distance.
7. The method of claim 6 wherein the third distance is less than or equal to about 10 μm.
8. The method of claim 6 wherein the third distance is equal to a diameter of each of the plurality of conductive vias.
9. A method of fabricating a stacked semiconductor device, the method comprising:
producing a plurality of semiconductor components, wherein producing each of the plurality of semiconductor components comprises:
forming an outer dielectric layer on a circuit side of a semiconductor substrate, the outer dielectric layer having a plurality of openings each aligned with an individual one of a plurality of conductive vias in the semiconductor substrate, wherein the plurality of conductive vias each extend from the circuit side to a back side opposite the circuit side;
etching the back side of the semiconductor substrate such that a terminal surface of a terminal portion of each of the plurality of conductive vias is at least a first distance from the back side;
depositing a polymer layer on the back side with a thickness such that an outer surface of the polymer layer is a second distance from the back side equal to or greater than the first distance;
planarizing the polymer layer and the terminal portion of each of the plurality of conductive vias to form a plurality of conductive contacts at the back side, wherein a bonding surface of each of the plurality of conductive contacts is the first distance from the back side, and wherein each of the plurality of conductive contacts is self-aligned with a corresponding one of the plurality of conductive vias; and
forming a plurality of terminal contacts, each of the plurality of terminal contacts coupled to one of the plurality of conductive contacts;
stacking a first semiconductor component of the plurality of semiconductor components on a second semiconductor component of the plurality of semiconductor components with the back side of the first semiconductor component facing the circuit side of the second semiconductor component; and
coupling each of the plurality of terminal contacts in the first semiconductor component to one of the plurality of conductive vias in the second semiconductor component.
10. The method of claim 9 wherein producing each of the plurality of semiconductor components further comprises forming a plurality of metallization layers over the circuit side of the semiconductor substrate, wherein each of the plurality of metallization layers is coupled to at least one of the plurality of conductive vias.
11. The method of claim 9 wherein coupling each of the plurality of terminal contacts in the first semiconductor component to one the plurality of conductive vias in the second semiconductor component comprises:
aligning each individual terminal contact of the first semiconductor component with an individual opening in the outer dielectric layer of the second semiconductor component; and
bonding each of the individual terminal contacts of the first semiconductor component with a corresponding conductive via exposed by the individual opening in the outer dielectric layer of the second semiconductor component.
12. The method of claim 9 wherein each of the plurality of terminal contacts includes a solder ball, and wherein coupling each of the plurality of terminal contacts in the first semiconductor component to one of the plurality of conductive vias in the second semiconductor component comprises reflowing the solder ball in each of the plurality of terminal contacts.
13. The method of claim 9 wherein producing each of the plurality of semiconductor components further comprises:
forming a plurality of back side redistribution conductors, each of the plurality of back side redistribution conductors coupled to an individual one of the plurality of conductive contacts; and
forming each of the plurality of terminal contacts on a corresponding one of the plurality of back side redistribution conductors.
14. The method of claim 9 wherein planarizing the back side of the semiconductor substrate comprises chemical mechanical planarization (CMP) and/or grinding.
15. The method of claim 9 wherein producing each of the plurality of semiconductor components further comprises thinning the semiconductor substrate from the back side prior to etching the back side of the semiconductor substrate.
16. A method for manufacturing a semiconductor device, the method comprising:
depositing a dielectric layer over an upper surface of a semiconductor substrate, the semiconductor substrate comprising a plurality of through substrate vias (TSVs) extending from the upper surface toward a lower surface of the semiconductor substrate, and wherein depositing the dielectric layer includes forming a plurality of openings each vertically aligned with a corresponding one of the plurality of TSVs;
removing portions of the semiconductor substrate from the lower surface such that a lower end of each of the plurality of TSVs protrudes from the lower surface by at least a first distance;
depositing a polymer layer on the lower surface with a thickness equal to or greater than the first distance to at least partially encapsulate the lower end of each of the plurality of TSVs;
planarizing the polymer layer and/or lower end of each of the plurality of TSVs to form a plurality of planarized contacts a second distance from the lower surface equal to or less than the first distance, wherein each of the plurality of planarized contacts is self-aligned with a corresponding one of the plurality TSVs; and
forming a plurality of terminal contacts, each of the plurality of terminal contacts coupled to one of the plurality of planarized contacts.
17. The method of claim 16 , further comprising forming one or more side redistribution conductors over the upper surface of the semiconductor substrate before depositing the dielectric layer, wherein each of the one or more side redistribution conductors is coupled to at least one of the plurality of TSVs at the upper surface.
18. The method of claim 16 wherein the first distance is between about 5 μm and about 10 μm, and wherein the thickness is between about 10 μm and about 25 μm.
19. The method of claim 16 , further comprising forming a plurality of back-side elements on the polymer layer each coupled between corresponding pairs of the plurality of terminal contacts and the plurality of planarized contacts.
20. The method of claim 16 , further comprising forming a plurality of under bump metallization layers between corresponding pairs of the plurality of terminal contacts and the plurality of planarized contacts.