Multiply accumulate (MAC) unit with split accumulator
In a multiply accumulate (MAC) unit, an accumulator may be implemented in two or more stages. For example, a first accumulator may accumulate products from the multiplier of the MAC unit, and a second accumulator may periodically accumulate the running total of the first accumulator. Each time the first accumulator's running total is accumulated by the second accumulator, the first accumulator may be initialized to begin a new accumulation period. In one embodiment, the number of values accumulated by the first accumulator within an accumulation period may be a user-adjustable parameter. In one embodiment, the bit width of the input of the second accumulator may be greater than the bit width of the output of the first accumulator. In another embodiment, an adder may be shared between the first and second accumulators, and a multiplexor may switch the accumulation operations between the first and second accumulators.
1. A device, comprising:
a multiplier;
a first accumulator configured to accumulate an output of the multiplier, wherein a floating point output of the first accumulator comprises a first exponent, e 1 , and a first mantissa, m 1 ; and
a second accumulator configured to accumulate an output of the first accumulator, wherein a floating point output of the second accumulator comprises a second exponent, e 2 , and a second mantissa, m 2 ,
wherein a bit width, m_bw 2 , of a portion of a storage element of the second accumulator that is allocated for storing the second mantissa, m 2 , is greater than a bit width, m_bw 1 , of a portion of a storage element of the first accumulator that is allocated for storing the first mantissa, m 1 .
2. The device of claim 1 , wherein a bit width, e_bw 2 , of a portion of the storage element of the second accumulator that is allocated for storing the second exponent, e 2 , is greater or equal to a bit width, e_bw 1 , of a portion of the storage element of the first accumulator that is allocated for storing the first exponent, e 1 .
3. The device of claim 1 , wherein the floating point output of the first accumulator is equal to 1·m 1 2 e 1 , and the floating point output of the second accumulator is equal to 1·m 2 2 e 2 .
4. The device of claim 3 , wherein the floating point input of the second accumulator comprises a third exponent, e 3 , and a third mantissa, m 3 , the device further comprising a floating point type converter configured to set the third mantissa, m 3 , equal to the first mantissa, right padded with m_bw 2 −m_bw 1 number of zeros.
5. The device of claim 1 , wherein the floating point output of the first accumulator further comprises a first sign, s 1 , and the floating point output of the second accumulator further comprises a second sign, s 2 .
6. The device of claim 5 , wherein the floating point output of the first accumulator is equal to (−1) s 1 1·m 1 2 e 1 , and the floating point output of the second accumulator is equal to (−1) s 2 1·m 2 2 e 2 .
7. The device of claim 5 , wherein the floating point input of the second accumulator comprises a third sign, s 3 , a third exponent, e 3 , and a third mantissa, m 3 , the device further comprising a floating point type converter configured to set the third sign, s 3 , equal to the first sign, s 1 , and the third mantissa, m 3 , equal to the first mantissa, m 1 , right padded with m_bw 2 -m_bw 1 number of zeros.
8. The device of claim 5 , wherein the first accumulator comprises a first exponent bias, λ 1 and the second accumulator comprises a second exponent bias, λ 2 .
9. The device of claim 8 , wherein the floating point output of the first accumulator is equal to (−1) s 1 1·m 1 2 e 1 λ 1 , and the floating point output of the second accumulator is equal to (−1) s 2 1·m 2 2 e 2 −λ 2 .
10. The device of claim 8 , wherein the floating point input of the second accumulator comprises a third sign, s 3 , a third exponent, e 3 , and a third mantissa, m 3 , the device further comprising a floating point type converter configured to set the third sign, s 3 , equal to the first sign, s 1 , the third exponent, e 3 , equal to e 1 −λ 1 +λ 2 , and the third mantissa, m 3 , equal to the first mantissa, m 1 , right padded with m_bw 2 −m_bw 1 number of zeros.
11. A method, comprising:
accumulating by a first accumulator an output of the multiplier, wherein a floating point output of the first accumulator comprises a first exponent, e 1 , and a first mantissa, m 1 ; and
accumulating by a second accumulator an output of the first accumulator, wherein a floating point output of the second accumulator comprises a second exponent, e 2 , and a second mantissa, m 2 ,
wherein a bit width, m_bw 2 , of a portion of a storage element of the second accumulator that is allocated for storing the second mantissa, m 2 , is greater than a bit width, m_bw 1 , of a portion of a storage element of the first accumulator that is allocated for storing the first mantissa, m 1 .
12. The method of claim 11 , wherein a bit width, e_bw 2 , of a portion of the storage element of the second accumulator that is allocated for storing the second exponent, e 2 , is greater than or equal to a bit width, e_bw 1 , of a portion of the storage element of the first accumulator that is allocated for storing the first exponent, e 1 .
13. The method of claim 11 , wherein the floating point output of the first accumulator is equal to 1·m 1 2 e 1 , and the floating point output of the second accumulator is equal to 1·m 2 2 e 2 .
14. The method of claim 13 , wherein the floating point input of the second accumulator comprises a third exponent, e 3 , and a third mantissa, m 3 , the method further comprising converting the floating point output of the first accumulator into the floating point input of the second accumulator by setting the third mantissa, m 3 , equal to the first mantissa, m 1 , right padded with m_bw 2 −m_bw 1 number of zeros.
15. The method of claim 11 , wherein the floating point output of the first accumulator further comprises a first sign, s 1 , and the floating point output of the second accumulator further comprises a second sign, s 2 .
16. The method of claim 15 , wherein the floating point output of the first accumulator is equal to (−1) s 1 1·m 1 2 e 1 , and the floating point output of the second accumulator is equal to (−1) s 2 1·m 2 2 e 2 .
17. The method of claim 15 , wherein the floating point input of the second accumulator comprises a third sign, s 3 , a third exponent, e 3 , and a third mantissa, m 3 , the method further comprising converting the floating point output of the first accumulator into the floating point input of the second accumulator by setting the third sign, s 3 , equal to the first sign, s 1 , and setting the third mantissa, m 3 , equal to the first mantissa, m 1 , right padded with m_bw 2 −m_bw 1 number of zeros.
18. The method of claim 15 , wherein the first accumulator comprises a first exponent bias, λ 1 and the second accumulator comprises a second exponent bias, λ 2 .
19. The method of claim 18 , wherein the floating point output of the first accumulator is equal to (−1) s 1 1·m 1 2 e 1 −λ 1 , and the floating point output of the second accumulator is equal to (−1) s 2 1·m 2 2 e 2 −λ 2 .
20. The method of claim 18 , wherein the floating point input of the second accumulator comprises a third sign, s 3 , a third exponent, e 3 , and a third mantissa, m 3 , the method further comprising converting the floating point output of the first accumulator into the floating point input of the second accumulator by setting the third sign, s 3 , equal to the first sign, s 1 , the third exponent, e 3 , equal to e 1 −λ 1 +λ 2 , and the third mantissa, m 3 , equal to the first mantissa, m 1 , right padded with m_bw 2 −m_bw 1 number of zeros.