Distributed multi-modal power maximizing integrated circuit for solar photovoltaic modules
Disclosed herein is add-on electronic circuit structures and methods for providing protection against reverse-electrical-current failures and for enabling comprehensive electrical (current-voltage sweep) and electro-optical (electroluminescence or EL using reserve current flow) testing of solar photovoltaic cells and modules having at least one multi-modal maximum-power-point tracking (MPPT) power optimizer integrated circuit chip to increase electrical energy generation yield of the modules. Such multi-modal MPPT power optimizer chips are used for distributed solar electric power generation enhancement in solar photovoltaic cells, modules, and systems under realistic operating conditions with non-ideal manufacturing and environmental variations (e.g., variable and/or non-uniform sunlight or daylight, mismatched cells, etc.).
1. A solar photovoltaic (PV) module for electric power generation, the module comprising:
a plurality of laminated strings of solar cells, each laminated string comprising a plurality of solar cells electrically connected together, and further comprising a positive lead and a negative lead; and
a plurality of multi-modal maximum-power-point tracking (MPPT) integrated circuits (ICs), each of said MPPT ICs having input terminals and output terminals, and having a pin structurally capable of enabling or disabling the MPPT IC function by the applied voltage on said pin being high or low, such that each laminated string of solar cells is connected to the input terminals of a corresponding MPPT IC via the laminated string's positive and negative leads;
wherein each of the plurality of MPPT ICs has an add-on electronic circuit for protection of the MPPT IC and module testability;
wherein each add-on electronic circuit comprises a reverse-current-flow protection circuit coupled across a corresponding MPPT IC;
wherein each reverse-current-flow protection circuit comprises an active bypass circuit, enabling module testing by bypassing and protecting the corresponding MPPT IC during reverse current flow opposite a photo-generated electrical current flow;
wherein each active bypass circuit comprises a transistor and a comparator;
wherein each add-on electronic circuit further comprises a Power-On-Reset (POR) circuit operating to disable a corresponding MPPT IC via its pin voltage.
2. The module of claim 1 , wherein the solar cells in each laminated string comprise crystalline silicon solar cells partitioned into smaller sub-cells.
3. The module of claim 2 , wherein an area of a sub-cell is one-half, one-third, or one-fourth of a full solar cell.
4. The module of claim 1 , wherein the plurality of MPPT ICs are connected together according to an output interconnection pattern.
5. The module of claim 4 , wherein the output interconnection pattern is an electrical series connection with the said output terminals of the plurality of MPPT ICs connected in electrical series.
6. The module of claim 4 , wherein the output interconnection pattern is a hybrid connection with said output terminals of the plurality of MPPT ICs connected in a combination of electrical series and parallel.
7. The module of claim 1 , wherein each reverse-current-flow protection circuit allows normal operation of a corresponding one of the MPPT ICs during PV power generation producing photo-generation electrical current flow.
8. The module of claim 1 , wherein each transistor provides a low-resistance reverse current flow path that bypasses the corresponding MPPT IC.
9. The module of claim 1 , wherein each transistor provides a high-resistance state as it remains off during normal photo-generation current flow, enabling normal operation of a corresponding MPPT IC.
10. The module of claim 1 , wherein each transistor is a p-channel FET.
11. The module of claim 1 , wherein each comparator detects reverse current flow and switches a corresponding transistor to its ON state to provide a low resistance path for reverse current flow, thereby bypassing and protecting a corresponding MPPT IC.
12. The module of claim 1 , wherein each comparator is electrically powered by a laminated string of solar cells coupled to the corresponding MPPT IC.
13. The module of claim 1 , wherein the MPPT ICs are enhanced with the add-on electronic circuits by monolithically integrating an add-on electronic circuit with an MPPT IC into the same package, or hybridly integrating an add-on electronic circuit to a separately packaged MPPT IC.
14. The module of claim 1 , wherein each POR circuit prevents and delays a corresponding MPPT IC from turning on or operating, by temporarily disabling the corresponding MPPT IC and turning on a corresponding bypass transistor, providing low-resistance path around the corresponding MPPT IC for photo-generated current flow during a module testing.
15. The module of claim 1 , wherein the module testing comprises a voltage sweep from short-circuit condition to open circuit condition or vice versa across output electrical terminals of the module.
16. The module of claim 1 , wherein each POR circuit detects a short-circuit or open circuit condition and turns on a corresponding bypass transistor while disabling a corresponding MPPT IC for a specified period of time to perform the module testing.
17. The module of claim 1 , wherein each add-on electronic circuit provides protection against reverse-current-flow failure of a corresponding MPPT IC.
18. The module of claim 17 , wherein each add-on electronic circuit enables electro-optical testing of the module.
19. The module of claim 18 , wherein the electro-optical testing comprises electro-luminescence testing.
20. The module of claim 18 , wherein said each transistor is a bypass filed effect transistor (FET) and each said comparator comprises electrical input leads that are connected to one of each of said input terminals and output terminals, and said comparator electrical input leads also connected to the source and drain of a corresponding bypass field-effect transistor (FET), with the combination of a comparator and a corresponding bypass field-effect transistor operating as reverse current flow detector and said reverse-current-flow protection circuit.