Digital device having a reset pad circuit that may be subject to hacker attack
A reset pad circuit has first and second inputs coupled, respectively, to a first reset access port receiving a first reset request and a second reset access port. The reset pad circuit generates a first reset state signal. An internal reset activation gate has inputs coupled to internal resources and an output that applies a reset request to the second reset access port. A memory element has first and second inputs coupled, respectively, to the output of the reset activation gate and the output of the reset pad circuit. The memory element generates a second reset state signal when receiving the reset request until receiving the first reset state signal. A reset forward gate coupled to outputs of the reset pad circuit and the memory element generates a system reset request in response to the first reset state signal or the second state signal.
1 . A digital device, comprising:
a reset pad circuit having a first input coupled to a first reset access port and configured to receive an external reset request, a second input coupled to a second reset access port and configured to receive an internal reset request, and an output, wherein the reset pad circuit is configured to generate a first reset state signal and includes a reset request propagating portion coupling the first and second inputs to the output of the reset pad circuit;
an internal reset activation gate having at least one input coupled to an internal resource and an output coupled to the second reset access port of reset pad circuit, wherein the internal reset activation gate is configured to generate the internal reset request;
a memory element having a first input coupled to the output of the internal reset activation gate, a second input coupled to the output of the reset pad circuit, and an output, wherein the memory element is configured to generate a second reset state signal when receiving the internal reset request until receiving the first reset state signal; and
a reset forwarding gate coupled to the output of the reset pad circuit and the output of the memory element and configured to generate a system reset request in response to one or more of the first reset state signal and the second reset state signal.
2 . The digital device according to claim 1 , wherein the reset forwarding gate is an AND gate.
3 . The digital device according to claim 1 , wherein the internal reset activation gate is an OR gate.
4 . The digital device according to claim 1 , wherein the memory element is one of a flip-flop or a latch.
5 . The digital device according to claim 4 , wherein the flip-flop is an asynchronous set, asynchronous reset D-type flip-flop having a data input coupled to a reference potential, a clock input coupled to the output of the internal reset activation gate and a set input coupled to the output of reset pad circuit.
6 . The digital device according to claim 4 , wherein the flip-flop is an S/R flip-flop, having a data input and a clock input coupled together and to a reference potential, a reset input coupled to the output of the internal reset activation gate and a set input coupled to the output of reset pad circuit.
7 . The digital device according claim 1 , further comprising an internal reset maintaining circuit activated by the internal reset activation gate and confirmed by the memory element, wherein the internal reset maintaining circuit is configured to generate an internal reset information supplied to the second input of the reset pad circuit.
8 . The digital device according to claim 7 , wherein the reset maintaining circuit is an OR gate having a first input coupled to the output of the internal reset activation gate, a second input coupled to the output of the memory element, and an output directly coupled with the second input of reset pad circuit.
9 . The digital device according to claim 1 , further comprising a state keeping element coupled to the second input of the memory element.
10 . The digital device according to claim 1 , further comprising a protective module:
wherein the memory element forms a first memory element that is configured to generate a second reset state signal;
a second memory element having a first input coupled to the output of the reset activation gate, a second input coupled to the output of the reset pad circuit, and an output, wherein the second memory element is configured to generate a second reset state signal having an opposite logical level than the second reset state signal generated by the first memory element when receiving the internal reset request until receiving the first reset state signal; and
an interrupt gate having a first input and a second input coupled, respectively, to outputs of the first and second memory elements and an output configured to generate a system reset in response to one or more of the second reset state signal generated by the first memory element and the second reset state signal generated by the second memory element.
11 . A method for activating a reset procedure of a digital device that includes a reset pad circuit, an internal reset activation gate, a memory element, and a reset forwarding gate, wherein the reset pad circuit has a first input configured to receive an external reset request, a second input configure to receive an internal reset request, and an output, the method comprising:
generating the internal reset request by the internal reset activation gate;
forwarding the internal reset request to a first input of the memory element and to the second input of the reset pad circuit;
generating, by the memory element, a reset state signal in response to receipt of the internal reset request;
activating, by the reset forwarding gate, a reset procedure in response to receipt of the reset state signal;
propagating the internal reset request in the reset pad circuit to generate a feedback reset state signal; and
deactivating, by the reset forwarding gate, the reset procedure in response to receipt of the feedback reset state signal.
12 . The method according to claim 11 , wherein deactivating the reset procedure comprises supplying the feedback reset state signal to a second input of the memory element.
13 . The method according to claim 12 , further comprising storing a logic level of the feedback reset state signal on a state keeping element coupled to the second input of the memory element.
14 . The method according to claim 11 , further comprising generating a reset information on the first input of the reset pad circuit based on the internal reset request.