TRANSISTOR ELEMENT, TERNARY INVERTER APPARATUS COMPRISING SAME, AND METHOD FOR PRODUCING SAME
A transistor device includes a substrate, a fin structure extending on the substrate in a direction parallel to a top surface of the substrate, a source region and a drain region provided at an upper portion of the fin structure, a constant current generating layer provided at a lower portion of the fin structure, a gate insulating film provided on both side surfaces and a top surface of the upper portion of the fin structure, and a gate electrode provided on the gate insulating film, wherein the gate electrode is provided on the fin structure and between the source region and the drain region, the constant current generating layer generates a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.
1 . A transistor device comprising:
a substrate;
a fin structure extending on the substrate in a direction parallel to a top surface of the substrate;
a source region and a drain region provided at an upper portion of the fin structure;
a constant current generating layer provided at a lower portion of the fin structure;
a gate insulating film provided on both side surfaces and a top surface of the upper portion of the fin structure; and
a gate electrode provided on the gate insulating film,
wherein the gate electrode is provided on the fin structure and between the source region and the drain region,
the constant current generating layer generates a constant current between the drain region and the substrate, and an electric field is formed between the drain region and the constant current generating layer, and
the constant current is independent from a gate voltage applied to the gate electrode and band-to-band tunneling (BTBT) current between the source region and the drain region.
2 . The transistor device of claim 1 , wherein the constant current generating layer is electrically connected to a lower portion of the source region and a lower portion of the drain region.
3 . The transistor device of claim 1 , wherein the constant current generating layer directly contacts a bottom surface of the source region and a bottom surface of the drain region.
4 . The transistor device of claim 1 , wherein
the substrate and the constant current generating layer have a first conductivity type, and
the source region and the drain region have a second conductivity type that is different from the first conductivity type.
5 . The transistor device of claim 4 , wherein a doping concentration of the constant current generating layer is 3×10 18 cm −3 or greater.
6 . The transistor device of claim 4 , wherein
an electric field is formed between the drain region and the constant current generating layer, and
an intensity of the electric field is 10 6 V/cm or greater.
7 . A ternary inverter device comprising:
an NMOS transistor device; and
a PMOS transistor device,
wherein each of the NMOS transistor device and the PMOS transistor device comprises: a substrate;
a fin structure extending on the substrate in a direction parallel to a top surface of the substrate;
a source region and a drain region provided at an upper portion of the fin structure;
a constant current generating layer provided under the fin structure,
wherein the constant current generating layer directly contacts a lower portion of the source region and a lower portion of the drain region, and generates a constant current between the drain region and the substrate, and
the drain region of the NMOS transistor device and the drain region of the PMOS transistor device have identical voltages
wherein an electric field is formed between the drain region and the constant current generating layer, and
the constant current is independent from a gate voltage applied to the gate electrode and band-to-band tunneling (BTBT) current between the source region and the drain region.
8 . The ternary inverter device of claim 7 , wherein each of the NMOS transistor device and the PMOS transistor device further comprises:
a gate insulating film provided on both side surfaces and a top surface of the upper portion of the fin structure; and
a gate electrode provided on the gate insulating film,
wherein the constant current is independent from a gate voltage applied to the gate electrode.
9 . The ternary inverter device of claim 7 , wherein
the drain region of the NMOS transistor device and the drain region of the PMOS transistor device have a first voltage when the NMOS transistor device has a channel current that is stronger than the constant current and the PMOS transistor device has the constant current that is stronger than a channel current, have a second voltage when the NMOS transistor device has the constant current that is stronger than the channel current and the PMOS transistor device has the channel current that is stronger than the constant current, and
have a third voltage when each of the NMOS transistor device and the PMOS transistor device has the constant current that is stronger than the channel current,
wherein the second voltage is greater than the first voltage, and the third voltage has a value between the first voltage and the second voltage.
10 . The ternary inverter device of claim 7 , wherein in each of the NMOS transistor device and the PMOS transistor device, the substrate and the constant current generating layer have conductivity types identical to each other, and a doping concentration of the constant current generating layer is greater than a doping concentration of the substrate.
11 . The ternary inverter device of claim 7 , wherein in each of the NMOS transistor device and the PMOS transistor device, a doping concentration of the constant current generating layer is 3×10 18 cm −3 or greater.