System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network
Representative apparatus, method, and system embodiments are disclosed for configurable computing. In a representative embodiment, a system includes an interconnection network, a processor, a host interface, and a configurable circuit cluster. The configurable circuit cluster may include a plurality of configurable circuits arranged in an array; an asynchronous packet network and a synchronous network coupled to each configurable circuit of the array; and a memory interface circuit and a dispatch interface circuit coupled to the asynchronous packet network and to the interconnection network. Each configurable circuit includes instruction or configuration memories for selection of a current data path configuration, a master synchronous network input, and a data path configuration for a next configurable circuit.
1. A system comprising:
an interconnection network;
a packet network;
a synchronous network;
a processor coupled to the interconnection network, the processor configured to generate and transmit a first work descriptor data packet on the interconnection network;
a plurality of configurable circuits arranged in an array, each configurable circuit of the plurality of configurable circuits coupled to the packet network and to the synchronous network, each configurable circuit of the plurality of configurable circuits comprising:
a configurable computation circuit; and
a configuration memory coupled to the configurable computation circuit;
a dispatch interface circuit coupled to the interconnection network and coupled through the packet network to the plurality of configurable circuits, the dispatch interface circuit comprising:
a plurality of registers; and
a plurality of logic circuits coupled to the plurality of registers, the plurality of logic circuits of the dispatch interface circuit arranged or configured, in response to receiving the first work descriptor data packet through the interconnection network, to generate and transmit on the packet network one or more data and control packets to one or more configurable circuits of the plurality of configurable circuits to configure the one or more configurable circuits for execution of a selected computation.
2. The system of claim 1 , wherein the configuration memory comprises:
a first instruction memory configured to store a first plurality of configuration instructions to configure the configurable computation circuit; and
a second instruction memory configured to store a second plurality of configuration instructions or instruction indices, the second plurality of configuration instructions or instruction indices comprising instructions or instruction indices for selection of a configuration instruction of the first plurality of configuration instructions from the first instruction memory and for selection of a synchronous network input from the synchronous network for receipt of the configuration instruction or a configuration instruction index from another configurable circuit of the plurality of configurable circuits of the array.
3. The system of claim 2 , wherein each configurable circuit, of the array of the plurality of configurable circuits, further comprises:
a configuration memory multiplexer coupled to the first instruction memory and to the second instruction memory, the configuration memory multiplexer having a selection input, wherein when the selection input has a first setting, the configuration instruction is selected from the first plurality of configuration instructions of the first instruction memory using a first configuration instruction or instruction index from the second instruction memory, and wherein when the selection input has a second setting, the second setting different from the first setting, the configuration instruction is selected using a second configuration instruction or instruction index, the second configuration instruction or instruction index received from the synchronous network input.
4. The system of claim 2 , wherein the second plurality of configuration instructions or instruction indices further comprises instructions or instruction indices for selection of a next configuration instruction or instruction index for output to a next configurable circuit of the plurality of configurable circuits.
5. The system of claim 4 , wherein each configurable circuit, of the plurality of configurable circuits, further comprises:
a conditional logic circuit coupled to the configurable computation circuit, the conditional logic circuit configured, depending upon an output from the configurable computation circuit, to modify the next configuration instruction or instruction index to output a modified next configuration instruction or instruction index to the next configurable circuit.
6. The system of claim 1 , wherein each configurable circuit, of the plurality of configurable circuits, further comprises:
a control circuit coupled to the configurable computation circuit, the control circuit comprising:
a plurality of control registers configured to store a completion table having a plurality of thread identifiers, having a corresponding data completion count for each thread identifier of the plurality of thread identifiers and, for each thread identifier for a current thread of the plurality of thread identifiers, having an identification of a last iteration or another thread identifier identifying a next thread for execution following execution of the current thread; and
a thread control circuit configured to self-schedule and queue a selected thread for execution when, for the thread identifier for the selected thread, the corresponding data completion count indicates completion of one or more data dependencies and the thread identifier for the selected thread is identified as the next thread for execution.
7. The system of claim 1 , wherein each configurable circuit, of the plurality of configurable circuits, further comprises:
a packet network input queue coupled to the packet network, the packet network input queue configured to receive a first message or packet from the packet network;
a packet network output queue coupled to the packet network, the packet network output queue configured to transfer a second message or packet for routing on the packet network;
and wherein the system further comprises:
a stop signal communication line coupled to each of the configurable circuits of the plurality of configurable circuits of the array; and
a flow control circuit coupled to the packet network output queue of each configurable circuit of the plurality of configurable circuits of the array, the flow control circuit configured to generate a stop signal on the stop signal communication line when a predetermined threshold has been reached in the packet network output queue;
wherein, in response to receipt of the stop signal, each configurable circuit of the plurality of configurable circuits of the array is configured to pause execution while continuing to receive one or more third messages or packets routed from the packet network.
8. The system of claim 1 , wherein the interconnection network is configured to use a split header and payload configuration for pipelining a plurality of communications or for delayed payload switching, and wherein the interconnection network is further configured to use a single header to route a plurality of data payloads as a sequential data burst.
9. The system of claim 1 , wherein each configurable circuit, of the plurality of configurable circuits, further comprises:
a plurality of synchronous network inputs; and
a plurality of synchronous network outputs;
wherein the synchronous network is configured to couple each synchronous network input of the plurality of synchronous network inputs to a corresponding synchronous network output, of the plurality of synchronous network outputs, of one or more adjacent configurable circuits of the plurality of configurable circuits of the array to form a plurality of direct connections between adjacent configurable circuits of the plurality of configurable circuits of the array, and wherein the synchronous network further comprises at least one pass through connection between adjacent configurable circuits of the plurality of configurable circuits of the array.
10. The system of claim 9 , wherein one or more configurable circuits of the plurality of the configurable circuits of the array are coupled in series through the synchronous network to form a first synchronous domain and one or more of the configurable circuits of the plurality of the configurable circuits of the array are coupled in series through the synchronous network to form a second synchronous domain, the plurality of configurable circuits of the array configured to perform a plurality of computations using the first and second synchronous domains, and the plurality of configurable circuits of the array further configured to generate and transmit a plurality of control messages over the packet network, the plurality of control messages comprising one or more completion messages and one or more continue messages.
11. The system of claim 1 , wherein the processor comprises:
a core control circuit comprising:
a thread control memory comprising a thread identifier register configured to store a plurality of thread identifiers, a program count register configured to store an initial program count, and a data cache configured to store a received argument or a general-purpose register configured to store the received argument;
an execution queue coupled to the thread control memory; and
a control logic and thread selection circuit coupled to the execution queue and to the thread control memory, the control logic and thread selection circuit configured, in response to a second work descriptor data packet having the initial program count and the received argument, to assign a thread identifier of the plurality of thread identifiers to an execution thread and to place the thread identifier in the execution queue, the control logic and thread selection circuit further configured to select the thread identifier for execution of the execution thread;
and
a processor core coupled to the core control circuit, the processor core configured to execute at least one instruction using the received argument for the execution thread, the at least one instruction corresponding to the initial program count.
12. The system of claim 11 , wherein the core control circuit further comprises:
an interconnection network interface coupled to the interconnection network and to the thread control memory, the interconnection network interface configured to receive the second work descriptor data packet and to decode the second work descriptor data packet into the initial program count for the execution thread and the received argument for the execution thread.
13. The system of claim 11 , wherein the core control circuit further comprises:
a network command queue coupled to the processor core; and
an interconnection network interface coupled to the interconnection network and to the network command queue;
wherein the processor core is configured to execute a fiber create instruction to generate and provide one or more commands to the network command queue, and wherein in response to the one or more commands in the network command queue, the interconnection network interface is configured to generate and transmit a plurality of call work descriptor data packets to the plurality of configurable circuits for execution of a corresponding plurality of execution threads.
14. The system of claim 11 , wherein the thread control memory further comprises a thread state register, the thread state register configured to store a valid status or a paused status for each thread identifier of the plurality of thread identifiers, and wherein the control logic and thread selection circuit is further configured to place the thread identifier in the execution queue when the thread identifier has the valid status, the control logic and thread selection circuit further configured, for as long as the valid status of the thread identifier remains, to periodically select the thread identifier in the execution queue for execution of an instruction of the execution thread by the processor core, and the control logic and thread selection circuit further configured to pause execution of the execution thread by not returning the thread identifier to the execution queue when the thread identifier has the paused status.
15. A system comprising:
an interconnection network;
a packet network;
a synchronous network;
a processor coupled to the interconnection network, the processor configured to execute a fiber create instruction and to generate and transmit a plurality of first work descriptor data packets on the interconnection network;
a network interface circuit coupled to the interconnection network, the network interface circuit configured to receive one or more first work descriptor data packets of the plurality of first work descriptor data packets;
a plurality of configurable circuits arranged in an array, each configurable circuit of the plurality of configurable circuits coupled to the packet network and to the synchronous network, each configurable circuit of the plurality of configurable circuits comprising:
a configurable computation circuit; and
a configuration memory coupled to the configurable computation circuit, the configuration memory comprising:
a first instruction memory configured to store a first plurality of configuration instructions to configure the configurable computation circuit; and
a second instruction memory configured to store a second plurality of configuration instructions or instruction indices, the second plurality of configuration instructions or instruction indices comprising instructions or instruction indices for selection of a configuration instruction of the first plurality of configuration instructions from the first instruction memory and for selection of a network input from the synchronous network for receipt of the configuration instruction or a configuration instruction index from another configurable circuit of the plurality of configurable circuits of the array;
and
a dispatch interface circuit coupled to the network interface circuit and coupled through the packet network to the plurality of configurable circuits of the array, the dispatch interface circuit comprising:
a plurality of registers; and
a plurality of logic circuits coupled to the plurality of registers, the plurality of logic circuits of the dispatch interface circuit arranged or configured, in response to receiving the one or more first work descriptor data packets from the network interface circuit, to generate and transmit on the packet network one or more data and control packets to one or more configurable circuits of the plurality of configurable circuits to configure the one or more configurable circuits for execution of a corresponding plurality of execution threads.
16. The system of claim 15 , wherein the processor comprises:
a core control circuit comprising:
a thread control memory comprising a thread identifier register configured to store a plurality of thread identifiers, a program count register configured to store an initial program count, and a data cache configured to store a received argument or a general-purpose register configured to store the received argument;
an execution queue coupled to the thread control memory; and
a control logic and thread selection circuit coupled to the execution queue and to the thread control memory, the control logic and thread selection circuit configured, in response to a second work descriptor data packet having the initial program count and the received argument, to assign a thread identifier of the plurality of thread identifiers to an execution thread and to place the thread identifier in the execution queue, the control logic and thread selection circuit further configured to select the thread identifier for execution of the execution thread;
and
a processor core coupled to the core control circuit, the processor core configured to execute at least one instruction using the received argument for the execution thread, the at least one instruction corresponding to the initial program count.
17. The system of claim 15 , wherein each configurable circuit, of the plurality of configurable circuits, further comprises:
a control circuit coupled to the configurable computation circuit, the control circuit comprising:
a plurality of control registers configured to store a completion table having a plurality of thread identifiers, having a corresponding data completion count for each thread identifier of the plurality of thread identifiers and, for each thread identifier for a current thread of the plurality of thread identifiers, having an identification of a last iteration or another thread identifier identifying a next thread for execution following execution of the current thread; and
a thread control circuit configured to self-schedule and queue a selected thread for execution when, for the thread identifier for the selected thread, the corresponding data completion count indicates completion of one or more data dependencies and the thread identifier for the selected thread is identified as the next thread for execution.
18. The system of claim 15 , wherein the interconnection network is configured to use a split header and payload configuration for pipelining a plurality of communications or for delayed payload switching, and wherein the interconnection network is further configured to use a single header to route a plurality of data payloads as a sequential data burst;
and wherein each configurable circuit, of the plurality of configurable circuits, further comprises:
a plurality of synchronous network inputs; and
a plurality of synchronous network outputs;
wherein the synchronous network is configured to couple each synchronous network input of the plurality of synchronous network inputs to a corresponding synchronous network output, of the plurality of synchronous network outputs, of one or more adjacent configurable circuits of the plurality of configurable circuits of the array to form a plurality of direct connections between adjacent configurable circuits of the plurality of configurable circuits of the array, and wherein the synchronous network further comprises at least one pass through connection between adjacent configurable circuits of the plurality of configurable circuits of the array.
19. The system of claim 15 , wherein the second plurality of configuration instructions or instruction indices further comprises instructions or instruction indices for selection of a next configuration instruction or instruction index for output to a next configurable circuit of the plurality of configurable circuits of the array; and
wherein each configurable circuit, of the plurality of configurable circuits, further comprises:
a conditional logic circuit coupled to the configurable computation circuit, the conditional logic circuit configured, depending upon an output from the configurable computation circuit, to modify the next configuration instruction or instruction index to output a modified next configuration instruction or instruction index to the next configurable circuit of the plurality of configurable circuits of the array.
20. A system comprising:
an interconnection network having a first plurality of communication lines for transmitting a packet header and a second plurality of communication lines for transmitting a data payload;
a packet network;
a synchronous network;
a processor coupled to the interconnection network, the processor comprising:
a processor core configured to execute a plurality of instructions; and
a core control circuit coupled to the processor core, the core control circuit configured to generate and transmit one or more work descriptor data packets on the interconnection network;
a plurality of configurable circuits arranged in an array, each configurable circuit of the plurality of configurable circuits coupled to the packet network and to the synchronous network, each configurable circuit of the plurality of configurable circuits comprising:
a plurality of synchronous network outputs;
a plurality of synchronous network inputs, each synchronous network input of the plurality of synchronous network inputs coupled to a corresponding synchronous network output, of the plurality of synchronous network outputs, of one or more adjacent configurable circuits of the plurality of configurable circuits of the array, to form a plurality of direct connections between adjacent configurable circuits of the plurality of configurable circuits of the array;
a configurable computation circuit; and
a configuration memory coupled to the configurable computation circuit, the configuration memory comprising:
a first instruction memory configured to store a first plurality of configuration instructions to configure the configurable computation circuit; and
a second instruction memory configured to store a second plurality of configuration instructions or instruction indices, the second plurality of configuration instructions or instruction indices comprising instructions or instruction indices for selection of a configuration instruction of the first plurality of configuration instructions from the first instruction memory and for selection of a synchronous network input from the plurality of synchronous network inputs for receipt of the configuration instruction or a configuration instruction index from another configurable circuit of the plurality of configurable circuits of the array;
and
a dispatch interface circuit coupled to the interconnection network and coupled through the packet network to the plurality of configurable circuits of the array, the dispatch interface circuit comprising:
a plurality of registers; and
a plurality of logic circuits coupled to the plurality of registers, the plurality of logic circuits of the dispatch interface circuit arranged or configured, in response to receiving the one or more work descriptor data packets, to generate and transmit on the packet network one or more data and control packets to one or more configurable circuits of the plurality of configurable circuits of the array to configure the one or more configurable circuits for execution of a corresponding plurality of execution threads.