Memory Device Comprising Electrically Floating Body Transistor

1 .- 18 . (canceled)

19 . An integrated circuit comprising:

a semiconductor memory array comprising a plurality of semiconductor memory cells, wherein each of said semiconductor memory cells comprises:

a memory transistor comprising:

a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions;

a first insulating region located above said floating body region;

second insulating regions adjacent to said floating body region; and

a buried layer region located below said floating body region and said second insulating regions and spaced from said second insulating regions so as not to contact said second insulating regions;

a third region in electrical contact with said buried layer region; and

a substrate region different from said third region and underlying said buried layer region;

wherein at least one of said floating body regions is integral with or connected to another of said floating body regions; and

a control circuit configured to apply back bias to said buried layer region.

20 . The integrated circuit of claim 19 , wherein said buried layer region is positioned between said substrate region and said floating body region.

21 . The integrated circuit of claim 19 , wherein said back bias is applied as a constant positive voltage bias.

22 . The integrated circuit of claim 19 , wherein said back bias is applied as a periodic pulse of positive voltage.

23 . The integrated circuit of claim 19 , wherein said buried layer region is configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell.

24 . The integrated circuit of claim 19 , comprising a fin structure.

25 . An integrated circuit comprising:

a semiconductor memory array comprising a plurality of semiconductor memory cells, wherein each of said semiconductor memory cells comprises:

a memory transistor comprising:

a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions;

a first insulating region located above said floating body region;

second insulating regions adjacent to said floating body region; and

a buried layer region located below said floating body region and said second insulating regions and spaced from said second insulating regions so as not to contact said second insulating regions;

wherein at least one of said floating body regions is integral with or connected to another of said floating body regions;

wherein a depletion region formed as a result of an application of a back bias to said buried layer region and at least one of said second insulating regions adjacent to said floating body region insulates said memory cell from an adjacent memory cell,

wherein application of said back bias results in at least two stable floating body charge levels; and

wherein said array further comprises a third region in electrical contact with said buried layer region, said third region having a conductivity type the same as a conductivity type of said buried layer; and

a control circuit configured to apply said back bias to said buried layer region.

26 . The integrated circuit of claim 25 , further comprising a substrate region, wherein said buried layer region is positioned between said substrate region and said floating body region.

27 . The integrated circuit of claim 25 , wherein said back bias is applied as a constant positive voltage bias.

28 . The integrated circuit of claim 25 , wherein said back bias is applied as a periodic pulse of positive voltage.

29 . The integrated circuit of claim 25 , wherein said buried layer region is configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell.

30 . The integrated circuit of claim 25 , comprising a fin structure.