Granted Patent B2

US 12,657,028 · App. 18/415,523 · Granted Jun 16, 2026

Inventor: Minhoo Kang (Seongnam-si, KR)

Assignee: Rebellions Inc.

G06F9/3802

Abstract

Claims (54)

1 . A neural processor comprising:

an instruction fetch unit, including a first program counter and a second program counter, that fetches instructions;

an instruction execution unit that generates control signals for executing the instructions fetched by the instruction fetch unit; and

a processing unit that computes a first data and a second data,

wherein the first program counter stores an address of a first instruction having a first dependency,

wherein the second program counter stores an address of a second instruction having a second dependency different from the first dependency,

wherein the instruction fetch unit fetches the first instruction by using the first program counter and fetches the second instruction by using the second program counter if execution of the first instruction has not been completed,

wherein the first instruction is an instruction for loading the first data and providing the first data to the processing unit, and

wherein the second instruction is an instruction for loading the second data and providing the second data to the processing unit; and

a memory in which a software program is stored, wherein the software program has information that the first instruction has the first dependency and the second instruction has the second dependency, and wherein the software program includes information on a start point of the first dependency, the first instruction, an end point of the first dependency, a start point of the second dependency, the second instruction, and an end point of the second dependency that are arranged sequentially.

2 . The neural processor of claim 1 , wherein the software program includes a header, the first instruction, and the second instruction, and

wherein the header includes information that the first instruction is included in the first dependency and information that the second instruction is included in the second dependency.

3 . The neural processor of claim 1 , wherein the software program includes the first instruction and the second instruction that are arranged sequentially,

wherein the first instruction includes an index bit for the first dependency, and

wherein the second instruction includes an index bit for the second dependency.

4 . The neural processor of claim 1 , wherein the first program counter stores an address of a third instruction having the first dependency if the instruction fetch unit fetches the first instruction.

5 . The neural processor of claim 4 , wherein the instruction fetch unit fetches the third instruction by using the first program counter if the execution of the first instruction is completed.

6 . The neural processor of claim 1 , further comprising a memory in which a software program is stored,

wherein the instruction fetch unit includes a plurality of program counters, and

wherein the software program includes information on a plurality of instructions to be fetched in the instruction fetch unit and dependency information on each of the plurality of instructions, and

wherein a number of the plurality of program counters is more than a number of the dependency information.

7 . A neural processing unit comprising:

a memory in which a software program storing first to third instructions is stored, wherein the software program stores the first to third instructions sequentially, wherein the first instruction and the second instruction have a first dependency, and the third instruction has a second dependency different from the first dependency, wherein the software program sequentially arranges the first instruction and the second instruction between information on a start point of the first dependency and information on an end point of the first dependency, and wherein the software program arranges the second instruction between information on a start point of the second dependency and information on an end point of the second dependency;

an instruction fetch unit, including a first program counter and a second program counter, that fetches an instruction in the software program;

an instruction execution unit that generates a control signal for executing the instruction fetched in the instruction fetch unit, and

a processing unit that computes a first data and a second data,

wherein the instruction fetch unit fetches the first instruction by using the first program counter storing an address of the first instruction in the software program and fetches, depending on completion of execution of the first instruction, any one of the second instruction or the third instruction by using the second program counter storing an address of the second instruction or the third instruction,

wherein a dependency of the second instruction is different from a dependency of the third instruction,

wherein the first instruction is an instruction for loading the first data and providing the first data to the processing unit, and

wherein the second instruction is an instruction for loading the second data and providing the second data to the processing unit.

8 . The neural processing unit of claim 7 , wherein the software program further stores a header, wherein the header includes information that the first instruction and the second instruction are included in the first dependency and information that the second instruction is included in the second dependency.

9 . The neural processing unit of claim 7 , wherein the first instruction includes an index bit related to the first dependency,

wherein the second instruction includes an index bit related to the first dependency, and

wherein the third instruction includes an index bit related to the second dependency.

10 . The neural processing unit of claim 7 , wherein the first instruction and the second instruction have a first dependency,

wherein the third instruction has a second dependency different from the first dependency,

wherein the instruction fetch unit fetches the second instruction if the execution of the first instruction is completed, and

wherein the instruction fetch unit fetches the third instruction if the execution of the first instruction has not been completed.

11 . The neural processing unit of claim 7 , wherein:

the first program counter stores an address of the second instruction, and

the second program counter stores an address of the third instruction.

12 . The neural processing unit of claim 7 , wherein the instruction fetch unit includes a plurality of program counters that store a plurality of instructions, and

wherein a number of dependencies for the plurality of instructions is less than or equal to a number of the plurality of program counters.

13 . A method for fetching instructions of a neural processor, performed by an instruction fetch unit included in a hardware block, wherein the instruction fetch unit including a first program counter and a second program counter fetches instructions and the instruction fetch unit is coupled to a processing unit that computes a first data and a second data, the method comprising:

fetching a first instruction by using the first program counter storing an address of the first instruction having a first dependency in a program;

fetching, depending on completion of execution of the first instruction, any one of a second instruction having a second dependency different from the first dependency or a third instruction having a first dependency,

wherein the second instruction is fetched by using the second program counter storing an address of the second instruction,

wherein the program comprises an instruction set arranged in order of the first instruction, the third instruction, and the second instruction, and information on the first dependency and the second dependency for the first instruction to the third instruction,

wherein the first instruction is an instruction for loading the first data and providing the first data to the processing unit,

wherein the second instruction is an instruction for loading the second data and providing the second data to the processing unit,

wherein the method further comprises determining dependencies of the first to third instructions by scanning information on the first dependency and the second dependency included in a header of the program.

14 . The method for fetching instructions of claim 13 , wherein the program includes information on a start point of the first dependency, an end point of the first dependency, a start point of the second dependency, and an end point of the second dependency,

wherein the first instruction and the second instruction are arranged between the start point of the first dependency and the end point of the second dependency, and

wherein the third instruction is arranged between the start point of the second dependency and the end point of the second dependency.

Assignments (1)

Priority Claims (2)

Continuity (2)

References Cited (19)