Decision feedback equalization taps and related apparatuses and methods
Decision feedback equalization (DFE) taps and related apparatuses and methods are disclosed. An apparatus includes a first electrically controllable switch, a second electrically controllable switch, and one or more delay elements. The first electrically controllable switch receives a history bit and selectively provides the history bit to gate terminals of first transistors of a DFE tap circuitry. The second electrically controllable switch receives a complementary history bit and selectively provides the complementary history bit to second gate terminals of second transistors of the DFE tap circuitry. The one or more delay elements provide one or more delayed data integration clock signals responsive to one or more data integration clock signals. A complementary delayed data integration clock signal controls switching of the first electrically controllable switch and the second electrically controllable switch.
1. An apparatus, comprising:
a decision feedback equalization (DFE) tap circuitry including a pair of transistors, the pair of transistors including drain terminals electrically connected to output nodes of the DFE tap circuitry, the pair of transistors including gate terminals to receive delayed complementary history bits; and
a gating circuitry electrically connected to the gate terminals of the pair of transistors, the gating circuitry to transition the DFE tap circuitry from a first logic state to a reset state, then from the reset state to a second logic state, the second logic state opposing the first logic state, wherein during the reset state a first non-zero portion of a common mode current flows through a first transistor of the pair of transistors and a second non-zero portion of the common mode current flows through a second transistor of the pair of transistors.
2. The apparatus of claim 1 , wherein the first non-zero portion of the common mode current and the second non-zero portion of the common mode current are each substantially equal to half the common mode current.
3. The apparatus of claim 1 , wherein the gating circuitry to deliver a common mode voltage potential to the gate terminals during the reset state.
4. The apparatus of claim 1 , wherein the gate terminals of the pair of transistors are both reset to a logic level zero or a logic level one responsive to a sampler reset state.
5. The apparatus of claim 1 , wherein the gating circuitry holds the tap circuitry in the reset state until after arrival of a history bit to avoid integrating a previous history bit.
6. The apparatus of claim 1 , wherein:
the gating circuitry delays data integration clock signals to align with arrival of a history bit, and gates responsive to the delayed data integration clock signals.
7. An apparatus comprising:
a decision feedback equalization (DFE) tap circuitry including:
a first pair of transistors including a first transistor and a second transistor;
a second pair of transistors including a third transistor and a fourth transistor;
the first and the third transistors including respective gate terminals to receive history bits; and
the second and the fourth transistors including respective gate terminals to receive complementary history bits; and
a gating circuitry electrically connected to the respective gate terminals of the first and the second pairs of transistors, the gating circuitry to place the DFE tap circuitry in a semi-wakeup state,
wherein, in the semi-wakeup state, the gating circuitry delivers a common mode voltage potential to the respective gate terminals of the first and the second pairs of transistors.
8. The apparatus of claim 7 , wherein:
the gating circuitry is to transition the DFE tap circuitry from the semi-wakeup state to an active state.
9. The apparatus of claim 7 , wherein:
the gating circuitry is to transition the DFE tap circuitry from an off state to the semi-wakeup state, then from the semi-wakeup state to an active state.
10. The apparatus of claim 7 , wherein:
the gating circuitry is to hold the DFE tap circuitry in the semi-wakeup state until after arrival of a history bit to avoid integrating a previous history bit.
11. The apparatus of claim 7 , wherein:
the gating circuitry is to delay data integration clock signals to align with arrival of a history bit and to gate responsive to the delayed data integration clock signals.
12. The apparatus of claim 7 , wherein:
the gating circuitry includes electrically controllable switches and delay elements to provide, in an active state of the DFE tap circuitry, the history bits as delayed history bits to the respective gate terminals of the first and the third transistors, and the complementary history bits as delayed complementary history bits to the respective gate terminals of the second and the fourth transistors.
13. The apparatus of claim 7 , wherein the DFE tap circuitry includes:
a first common mode current source;
a second common mode current source;
a first pull-down current source;
a second pull-down current source;
the first transistor including a drain terminal electrically connected to the first common mode current source and a source terminal electrically connected to the first pull-down current source;
the second transistor including a drain terminal electrically connected to the second common mode current source and a source terminal electrically connected to the first pull-down current source;
the third transistor including a drain terminal electrically connected to the second common mode current source and a source terminal electrically connected to the second pull-down current source; and
the fourth transistor including a drain terminal electrically connected to the first common mode current source and a source terminal electrically connected to the second pull-down current source.
14. The apparatus of claim 7 , wherein:
in the semi-wakeup state in which the common mode voltage potential is delivered to the respective gate terminals of the first and the second pairs of transistors, substantially half of a first total current flows through the first transistor and substantially the other half of the first total current flows through the second transistor, and substantially half of a second total current flows through the third transistor and substantially the other half of the second total current flows through the fourth transistor.
15. An apparatus comprising:
a decision feedback equalization (DFE) tap circuitry including:
a first common mode current source;
a second common mode current source;
a first pull-down current source;
a second pull-down current source;
a first pair of transistors including a first transistor electrically connected from the first common mode current source to the first pull-down current source and a second transistor electrically connected from the second common mode current source to the first pull-down current source;
a second pair of transistors including a third transistor electrically connected from the second common mode current source to the second pull-down current source and a fourth transistor electrically connected from the first common mode current source to the second pull-down current source;
a first output node electrically connected between the first common mode current source and drain terminals of the first and the fourth transistors; and
a second output node electrically connected between the second common mode current source and drain terminals of the second and the third transistors; and
a gating circuitry electrically connected to gate terminals of the first and the second pairs of transistors, the gating circuitry to deliver a common mode voltage potential to gate terminals of the first and the second pairs of transistors.
16. The apparatus of claim 15 , wherein:
the gating circuitry delivers the common mode voltage potential to the gate terminals of the first and the second pairs of transistors in a semi-wakeup state, the semi-wakeup state in between an off state and an active state of the DFE tap circuitry.
17. The apparatus of claim 16 , wherein:
the gating circuitry is to transition the DFE tap circuitry from the semi-wakeup state to the active state.
18. The apparatus of claim 16 , wherein:
the gating circuitry is to transition the DFE tap circuitry from the off state to the semi-wakeup state, then from the semi-wakeup state to the active state.
19. The apparatus of claim 16 , wherein:
the gating circuitry is to hold the DFE tap circuitry in the semi-wakeup state until after arrival of a history bit to avoid integrating a previous history bit.
20. The apparatus of claim 16 , wherein:
in the semi-wakeup state in which the common mode voltage potential is delivered to the gate terminals of the first and the second pairs of transistors, substantially half of a first total current flows through the first transistor and substantially the other half of the first total current flows through the second transistor, and substantially half of a second total current flows through the third transistor and substantially the other half of the second total current flows through the fourth transistor.