Granted Patent B2

US 12,620,895 · App. 18/418,760 · Granted May 5, 2026

Inventors: Marco La Pila (Gravina di Catania, IT); Giuseppe Platania (Valverde, IT); Placido Salvatore Battiato (Biancavilla, IT)

Assignee: STMicroelectronics International N.V.

H02M3/07H03K4/06H02M1/0095

Abstract

Claims (110)

1 . A DC-DC converter, comprising:

a power stage comprising:

a first high-side transistor coupled between an input voltage and a high-side tap, a second high-side transistor coupled between the high-side tap and an output tap, a first low-side transistor coupled between a low-side tap and ground, and a second low-side transistor coupled between the output tap and the low-side tap;

a flying capacitor coupled between the high-side tap and the low-side tap;

an inductor coupled between the output tap and an output node;

an output capacitor coupled between the output node and ground; and

a feedback divider coupled in parallel with the output capacitor, with a feedback voltage being formed at a tap of the feedback divider;

a ramp generator configured to generate a first ramp signal and a second ramp signal, wherein the ramp generator generates the first ramp signal as a function of a constant reference voltage and generates the second ramp signal as a function of a difference between a voltage across the flying capacitor and one half the input voltage;

control circuitry configured to:

generate an error signal based on a comparison between the feedback voltage and a reference voltage;

generate a first high-side control signal for the first high-side transistor, and a first low-side control signal for the first low-side transistor, based on a comparison between the first ramp signal and the error signal; and

generate a second high-side control signal for the second high-side transistor, and a second low-side control signal for the second low-side transistor, based on a comparison between the second ramp signal and the error signal.

2 . The DC-DC converter of claim 1 , wherein the ramp generator comprises:

first ramp generation circuitry comprising:

a first voltage-to-current converter configured to generate a first charging current based upon the constant reference voltage;

a first timing capacitor configured to be charged by the first charging current; and

a first reset transistor configured to discharge the first timing capacitor at a first edge of a clock signal;

wherein the first ramp signal is generated as a function of the charging and discharging of the first timing capacitor.

3 . The DC-DC converter of claim 2 , wherein the first voltage-to-current converter comprises:

a first amplifier having a non-inverting input receiving the constant reference voltage, an inverting input coupled to ground through a first sense resistor, and an output;

a first n-channel transistor having a source coupled to ground through the first sense resistor, a gate coupled to the output of the first amplifier, and a drain;

a first p-channel transistor having a source coupled to a supply voltage, a drain coupled to the drain of the first n-channel transistor, and a gate coupled to the drain of the first p-channel transistor;

a second p-channel transistor having a source coupled to the supply voltage, a drain coupled to the first timing capacitor, and a gate coupled to the gate of the first p-channel transistor; and

a second n-channel transistor having a drain coupled to the first timing capacitor, a source coupled to ground, and a gate coupled to a first reset signal, assertion of the first reset signal corresponding to the first edge of the clock signal.

4 . The DC-DC converter of claim 2 , wherein the ramp generator further comprises:

second ramp generation circuitry comprising:

a second voltage-to-current converter configured to generate a second charging current based upon the difference between the voltage across the flying capacitor and one half the input voltage;

a second timing capacitor configured to be charged by the second charging current; and

a second reset transistor configured to discharge the second timing capacitor at a second edge of the clock signal;

wherein the second ramp signal is generated as a function of the charging and discharging of the second timing capacitor.

5 . The DC-DC converter of claim 4 , wherein the second voltage-to-current converter comprises:

a second amplifier having a non-inverting input receiving a delta voltage whose slope is proportional to the difference between one half the input voltage and the voltage across the flying capacitor, an inverting input coupled to ground through a second sense resistor, and an output;

a third n-channel transistor having a source coupled to ground through the second sense resistor, a gate coupled to the output of the second amplifier, and a drain;

a third p-channel transistor having a source coupled to a supply voltage, a drain coupled to the drain of the third n-channel transistor, and a gate coupled to the drain of the third p-channel transistor;

a fourth p-channel transistor having a source coupled to the supply voltage, a drain coupled to the second timing capacitor, and a gate coupled to the gate of the third p-channel transistor; and

a fourth n-channel transistor having a drain coupled to the second timing capacitor, a source coupled to ground, and a gate coupled to a second reset signal, assertion of the second reset signal corresponding to the second edge of the clock signal.

6 . The DC-DC converter of claim 4 , further comprising balancing circuitry, the balancing circuitry comprising an amplifier having a first input coupled to receive one half the input voltage, a second input coupled to the voltage across the flying capacitor through a balance resistor, and an output coupled to the second input through a balance capacitor, wherein a delta voltage is generated at the output of the amplifier, the delta voltage having a slope that is proportional to the difference between one half the input voltage and the voltage across the flying capacitor; and wherein the second voltage-to-current converter generates the second charging current based upon the delta voltage.

7 . The DC-DC converter of claim 4 , further comprising balancing circuitry, the balancing circuitry comprising an amplifier having a non-inverting input coupled to receive one half the input voltage, an inverting input coupled to the voltage across the flying capacitor through a balance resistor, and an output coupled to the inverting input through a balance capacitor, wherein a delta voltage is generated at the output of the amplifier, the delta voltage having a slope that is proportional to the difference between one half the input voltage and the voltage across the flying capacitor; and wherein the second voltage-to-current converter generates the second charging current based upon the delta voltage.

8 . A method of operating a DC-DC converter, the method comprising:

converting an input voltage to an output voltage using a power stage;

generating a first ramp signal as a function of a constant reference voltage;

generating a second ramp signal as a function of a difference between one half the input voltage and a voltage across a flying capacitor of the power stage;

generating an error signal based on a comparison between a reference voltage and a feedback voltage representative of the output voltage;

generating a first high-side control signal for a first high-side transistor of the power stage, and a first low-side control signal for a first low-side transistor of the power stage, based on a comparison between the first ramp signal and the error signal; and

generating a second high-side control signal for a second high-side transistor of the power stage, and a second low-side control signal for a second low-side transistor of the power stage, based on a comparison between the second ramp signal and the error signal.

9 . The method of claim 8 , wherein generating the first ramp signal comprises:

generating a first charging current based upon the constant reference voltage;

receiving the first charging current to charge a first timing capacitor; and

discharging the first timing capacitor at a first edge of a clock signal;

wherein the first ramp signal is generated as a function of the charging and discharging of the first timing capacitor.

10 . The method of claim 9 , wherein generating the second ramp signal comprises:

generating a second charging current based on a delta voltage whose slope is proportional to a difference between one half the input voltage and the voltage across the flying capacitor;

receiving the second charging current to charge a second timing capacitor;

discharging the second timing capacitor at a second edge of the clock signal;

wherein the second ramp signal is generated as a function of the charging and discharging of the second timing capacitor.

11 . A DC-DC converter, including:

a power stage configured to convert an input voltage to an output voltage;

a ramp generator configured to:

generate a first ramp signal as a function of a constant reference voltage; and

generate a second ramp signal as a function of a difference between one half the input voltage and a voltage across a flying capacitor of the power stage;

an error amplifier configured to generate an error signal based on a comparison between a reference voltage and a feedback voltage representative of the output voltage; and

control circuitry configured to:

generate a first high-side control signal for a first high-side transistor of the power stage, and a first low-side control signal for a first low-side transistor of the power stage, based on a comparison between the first ramp signal and the error signal; and

generate a second high-side control signal for a second high-side transistor of the power stage, and a second low-side control signal for a second low-side transistor of the power stage, based on a comparison between the second ramp signal and the error signal.

12 . The DC-DC converter of claim 11 , wherein the ramp generator generates the first ramp signal by:

generating a first charging current based upon the constant reference voltage;

receiving the first charging current to charge a first timing capacitor; and

discharging the first timing capacitor at a first edge of a clock signal; and

wherein the first ramp signal is generated as a function of the charging and discharging of the first timing capacitor.

13 . The DC-DC converter of claim 12 , wherein the ramp generator generates the second ramp signal by:

generating a second charging current based on a delta voltage whose slope is proportional to a difference between one half the input voltage and the voltage across the flying capacitor;

receiving the second charging current to charge a second timing capacitor; and

discharging the second timing capacitor at a second edge of the clock signal;

wherein the second ramp signal is generated as a function of the charging and discharging of the second timing capacitor.

14 . A DC-DC converter, comprising:

a power stage comprising:

a first high-side transistor coupled between an input voltage and a high-side tap, a second high-side transistor coupled between the high-side tap and an output tap, a first low-side transistor coupled between a low-side tap and ground, and a second low-side transistor coupled between the output tap and the low-side tap;

a flying capacitor coupled between the high-side tap and the low-side tap;

an inductor coupled between the output tap and an output node;

an output capacitor coupled between the output node and ground; and

a feedback divider coupled in parallel with the output capacitor, with a feedback voltage being formed at a tap of the feedback divider;

a ramp generator comprising:

first ramp generation circuitry comprising:

a first voltage-to-current converter configured to generate a first charging current based upon a constant reference voltage;

a first timing capacitor configured to be charged by the first charging current; and

a first reset transistor configured to discharge the first timing capacitor at a first edge of a clock signal;

wherein a first ramp signal is generated as a function of the charging and discharging of the first timing capacitor; and

wherein the first voltage-to-current converter comprises:

a first amplifier having a non-inverting input receiving the constant reference voltage, an inverting input coupled to ground through a first sense resistor, and an output;

a first n-channel transistor having a source coupled to ground through the first sense resistor, a gate coupled to the output of the first amplifier, and a drain;

a first p-channel transistor having a source coupled to a supply voltage, a drain coupled to the drain of the first n-channel transistor, and a gate coupled to the drain of the first p-channel transistor;

a second p-channel transistor having a source coupled to the supply voltage, a drain coupled to the first timing capacitor, and a gate coupled to the gate of the first p-channel transistor; and

a second n-channel transistor having a drain coupled to the first timing capacitor, a source coupled to ground, and a gate coupled to a first reset signal, assertion of the first reset signal corresponding to the first edge of the clock signal;

second ramp generation circuitry comprising:

a second voltage-to-current converter configured to generate a second charging current based upon a difference between a voltage across the flying capacitor and one half the input voltage;

a second timing capacitor configured to be charged by the second charging current; and

a second reset transistor configured to discharge the second timing capacitor at a second edge of the clock signal;

wherein a second ramp signal is generated as a function of the charging and discharging of the second timing capacitor;

wherein the second voltage-to-current converter comprises:

a second amplifier having a non-inverting input receiving a delta voltage whose slope is proportional to the difference between one half the input voltage and the voltage across the flying capacitor, an inverting input coupled to ground through a second sense resistor, and an output;

a third n-channel transistor having a source coupled to ground through the second sense resistor, a gate coupled to the output of the second amplifier, and a drain;

a third p-channel transistor having a source coupled to the supply voltage, a drain coupled to the drain of the third n-channel transistor, and a gate coupled to the drain of the third p-channel transistor;

a fourth p-channel transistor having a source coupled to the supply voltage, a drain coupled to the second timing capacitor, and a gate coupled to the gate of the third p-channel transistor; and

a fourth n-channel transistor having a drain coupled to the second timing capacitor, a source coupled to ground, and a gate coupled to a second reset signal, assertion of the second reset signal corresponding to the second edge of the clock signal;

control circuitry configured to:

generate an error signal based on the feedback voltage and a reference voltage;

generate a first high-side control signal for the first high-side transistor, and a first low-side control signal for the first low-side transistor, based on the first ramp signal and the error signal; and

generate a second high-side control signal for the second high-side transistor, and a second low-side control signal for the second low-side transistor, based on the second ramp signal and the error signal.

15 . The DC-DC converter of claim 14 , further comprising balancing circuitry, the balancing circuitry comprising an amplifier having a first input coupled to receive one half the input voltage, a second input coupled to the voltage across the flying capacitor through a balance resistor, and an output coupled to the second input through a balance capacitor, wherein the delta voltage is generated at the output of the amplifier, the delta voltage having a slope that is proportional to the difference between one half the input voltage and the voltage across the flying capacitor; and wherein the second voltage-to-current converter generates the second charging current based upon the delta voltage.

16 . The DC-DC converter of claim 14 , further comprising balancing circuitry, the balancing circuitry comprising an amplifier having a non-inverting input coupled to receive one half the input voltage, an inverting input coupled to the voltage across the flying capacitor through a balance resistor, and an output coupled to the inverting input through a balance capacitor, wherein the delta voltage is generated at the output of the amplifier, the delta voltage having a slope that is proportional to the difference between one half the input voltage and the voltage across the flying capacitor; and wherein the second voltage-to-current converter generates the second charging current based upon the delta voltage.

Assignments (2)

Continuity (1)

References Cited (11)