IP Library Patent Application 18420024
Patent Application
App. No. 18/420,024

EMBEDDED SECURE CIRCUIT

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Quick Facts
Patent No.
US None
App. No.
18/420,024
Abstract

The present description concerns an integrated circuit comprising at least two secure circuits having similar functions but respecting or complying with different security schemes.

Claims (40)

1 . An integrated circuit comprising:

at least two secure circuits having similar functions but complying with different security schemes.

2 . The integrated circuit according to claim 1 , wherein each secure circuit is configured for a respective certification authority.

3 . The integrated circuit according to claim 1 , wherein each secure circuit is configured according to a geographical area.

4 . The integrated circuit according to claim 1 , further comprising:

a selector having a control terminal coupled to a terminal of the integrated circuit; and

one or more communication buses accessible to the at least two secure circuits via the selector.

5 . The integrated circuit according to claim 1 , further comprising other circuits shared between the at least two secure circuits.

6 . The integrated circuit according to claim 1 , further comprising communication and input/output circuits accessible to the at least two secure circuits.

7 . The integrated circuit according to claim 1 , further comprising one or more power management units accessible to the at least two secure circuits.

8 . The integrated circuit according to claim 1 , further comprising one or more clock generation circuits accessible to the at least two secure circuits.

9 . The integrated circuit according to claim 1 , wherein the integrated circuit is configured to select one of the at least two secure circuits in accordance with a software control originating from an outside of the integrated circuit.

10 . The integrated circuit according to claim 1 , wherein each secure circuit comprises:

at least one secure circuit communication bus;

at least one non-volatile memory coupled to the at least one secure circuit communication bus;

at least one volatile memory coupled to the at least one secure circuit communication bus;

at least one peripheral circuit, dedicated to features required by a respective certification authority, coupled to the at least one secure circuit communication bus; and

a microprocessor communicatively coupled, via the at least one secure circuit communication bus, to the at least one non-volatile memory, the at least one volatile memory, and the at least one peripheral circuit.

11 . An electronic system comprising:

at least one communication bus;

at least one memory coupled to the at least one communication bus;

at least one input/output interface coupled to the at least one communication bus;

an integrated circuit coupled to the at least one communication bus, and comprising at least two secure circuits having similar functions but complying with different security schemes; and

a microcontroller communicatively coupled, via the at least one communication bus, to the at least one memory, the at least one input/output interface, and the integrated circuit.

12 . The electronic system according to claim 11 , wherein each secure circuit is configured for a respective certification authority.

13 . The electronic system according to claim 11 , wherein each secure circuit is configured according to a geographical area.

14 . The electronic system according to claim 11 , wherein the integrated circuit further comprises:

a selector having a control terminal coupled to a terminal of the integrated circuit; and

one or more communication buses accessible to the at least two secure circuits via the selector.

15 . The electronic system according to claim 11 , wherein the integrated circuit further comprises other circuits shared between the at least two secure circuits.

16 . The electronic system according to claim 11 , wherein the integrated circuit further comprises communication and input/output circuits accessible to the at least two secure circuits.

17 . The electronic system according to claim 11 , wherein the integrated circuit further comprises one or more power management units accessible to the at least two secure circuits.

18 . The electronic system according to claim 11 , wherein the integrated circuit further comprises one or more clock generation circuits accessible to the at least two secure circuits.

19 . The electronic system according to claim 11 , wherein the integrated circuit is configured to select one of the at least two secure circuits in accordance with a software control originating from an outside of the integrated circuit.

20 . The electronic system according to claim 11 , wherein each secure circuit comprises:

at least one secure circuit communication bus;

at least one non-volatile memory coupled to the at least one secure circuit communication bus;

at least one volatile memory coupled to the at least one secure circuit communication bus;

at least one peripheral circuit, dedicated to features required by a respective certification authority, coupled to the at least one secure circuit communication bus; and

a microprocessor communicatively coupled, via the at least one secure circuit communication bus, to the at least one non-volatile memory, the at least one volatile memory, and the at least one peripheral circuit.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2024
From: STMICROELECTRONICS (ROUSSET) SAS
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 067179/0080 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 23, 2024
From: TRAMONI, ALEXANDRE; ROMAIN, FABRICE
To: STMICROELECTRONICS (ROUSSET) SAS
Reel/Frame 066215/0135 →