Reset circuit

1. A circuit for resetting an electronic device that comprises at least two electronic components, said circuit for resetting comprising:

a parity control circuit;

at least two first flip-flops, each first flip-flop comprising an output coupled to at least one of said at least two electronic components; and

at least two second flip-flops, each second flip-flop comprising at least one output coupled to an input of said parity control circuit.

2. The circuit according to claim 1 , further comprising a control circuit configured to deliver a reset control signal, wherein each flip-flop of said at least two first and second flip-flops is controlled by said reset signal.

3. The circuit according to claim 2 , wherein each flip-flop of said at least two first and second flip-flops comprises at least one reset input receiving the reset control signal.

4. The circuit according to claim 1 , wherein each flip-flop of said at least two second flip-flops comprises at least one input configured to receive a power supply voltage.

5. The circuit according to claim 1 , wherein each flip-flop of said at least two second flip-flops is placed at a distance shorter than a critical distance from one first flip-flop of the at least two first flip-flops.

6. The circuit according to claim 5 , wherein said critical distance is a minimum length of a metal track for which a pulse is recognizable as being a control pulse by said at least two first flip-flops.

7. The circuit according to claim 6 , wherein said pulse is recognizable as being a control pulse when its time duration is longer than a minimum duration and/or when a value of its amplitude is greater than a minimum value.

8. The circuit according to claim 1 , wherein at least one second flip-flop of said at least two second flip-flops is associated with a plurality of first flip-flops of said at least two first flip-flops.

9. The circuit according to claim 1 , wherein each flip-flop of said at least two first and second flip-flops is a D-type flip-flop.

10. The electronic device, comprising said reset circuit according to claim 1 .

11. A method of detecting a partial reset attack using said reset circuit according to claim 1 , said method comprising:

detecting when said at least two second flip-flops have different states; and

then signaling with said parity control circuit an anomaly.

12. The method according to claim 11 , further comprising, in response to said parity control circuit signaling the anomaly, requesting by a control circuit a resetting of said device.

13. The circuit according to claim 1 , wherein the parity control circuit is configured to detect when the outputs said at least two second flip-flops have different states, and in response thereto signal an anomaly.

14. A circuit, comprising:

a plurality of electronic components;

wherein each electronic component has a reset input;

a plurality of first flip-flops coupled to a reset line;

wherein each first flip-flop has an output coupled to the reset input of a corresponding electronic component;

a plurality of second flip-flops coupled to the reset line;

a first logic circuit configured to logically combine signals output from the plurality of second flip-flops;

a second logic circuit configured to logically combine a signal output from the first logic circuit and a reset signal, wherein an output signal from the second logic circuit is applied to the reset line.

15. The circuit according to claim 14 , wherein each second flip-flop is placed at a distance shorter than a critical distance from one of the plurality of first flip-flops.

16. The circuit according to claim 15 , wherein said critical distance is a minimum length of a metal track for which a pulse is recognizable as being a control pulse by said at least two first flip-flops.

17. The circuit according to claim 16 , wherein said pulse is recognizable as being a control pulse when its time duration is longer than a minimum duration.

18. The circuit according to claim 16 , wherein said pulse is recognizable as being a control pulse when a value of its amplitude is greater than a minimum value.

19. The circuit according to claim 14 , further comprising a pulse stretch circuit configured to control a stretch of the signal output from the first logic circuit.

20. The circuit according to claim 14 , further comprising:

a node configured to receive the reset signal; and

a pull down transistor connected said node and controlled in response to the signal output from the first logic circuit.

21. The circuit according to claim 20 , further comprising: a buffering circuit configured to buffer the reset signal before application to the second logic circuit.

22. The circuit according to claim 14 , further comprising: a spike filter configured to filter the output signal from the second logic circuit.